VHDL Code for SR, JK, and T Flip-Flops

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SR Flip-Flop Logic Diagram SR Flip-Flop Truth Table

VHDL Code for SR Flip-Flop

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library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;

entity SR_FF is
PORT( S, R, CLOCK: in std_logic;
      Q, QBAR: out std_logic);
end SR_FF;

Architecture behavioral of SR_FF is
begin
  PROCESS(CLOCK)
  variable tmp: std_logic;
  begin
    if(CLOCK='1' and CLOCK'EVENT) then
      if(S='0' and R='0')then
        tmp:=tmp;
      elsif(S='1' and R='1')then
        tmp:='Z';
      elsif(S='0' and R='1')then
        tmp:='0';
      else
        tmp:='1';
      end if;
    end if;
    Q <= tmp;
    QBAR <= not tmp;
  end PROCESS;
end behavioral;

JK Flip-Flop Logic Diagram JK Flip-Flop Truth Table

VHDL Code for JK Flip-Flop

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library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;

entity JK_FF is
PORT( J, K, CLOCK: in std_logic;
      Q, QB: out std_logic);
end JK_FF;

Architecture behavioral of JK_FF is
begin
  PROCESS(CLOCK)
  variable TMP: std_logic;
  begin
    if(CLOCK='1' and CLOCK'EVENT) then
      if(J='0' and K='0')then
        TMP:=TMP;
      elsif(J='1' and K='1')then
        TMP:= not TMP;
      elsif(J='0' and K='1')then
        TMP:='0';
      else
        TMP:='1';
      end if;
    end if;
    Q <= TMP;
    QB <= not TMP;
  end PROCESS;
end behavioral;


JK Flip-Flop Logic Diagram Duplicate JK Flip-Flop Truth Table Duplicate

VHDL Code for JK Flip-Flop (Alternative Implementation)

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library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;

entity JK_FF is
PORT( J, K, CLOCK: in std_logic;
      Q, QB: out std_logic);
end JK_FF;

Architecture behavioral of JK_FF is
begin
  PROCESS(CLOCK)
  variable TMP: std_logic;
  begin
    if(CLOCK='1' and CLOCK'EVENT) then
      if(J='0' and K='0')then
        TMP:=TMP;
      elsif(J='1' and K='1')then
        TMP:= not TMP;
      elsif(J='0' and K='1')then
        TMP:='0';
      else
        TMP:='1';
      end if;
    end if;
    Q <= TMP;
    QB <= not TMP;
  end PROCESS;
end behavioral;


T Flip-Flop Logic Diagram T Flip-Flop Truth Table

VHDL Code for T Flip-Flop

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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity T_FF is
port( T: in std_logic;
      Clock: in std_logic;
      Q: out std_logic);
end T_FF;

architecture Behavioral of T_FF is
signal tmp: std_logic;
begin
  process (Clock)
  begin
    if Clock'event and Clock='1' then
      if T='0' then
        tmp <= tmp;
      elsif T='1' then
        tmp <= not (tmp);
      end if;
    end if;
  end process;
  Q <= tmp;
end Behavioral;
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Tags:
SR Flip-Flop Sequential Circuits FPGA Logic Design Hardware Description Language Electronics Digital Logic VHDL T Flip-Flop JK Flip-Flop Truth Tables