Reliable High-Speed Digital Design for Embedded Hardware

Introduction to Reliable Embedded Systems

Dr. Michael P. Hayes
ENCE 461: Embedded Systems II
Electrical and Computer Engineering

So you want to build an embedded system? And you want to make the hardware reliable? Oh, and you want to be able to meet EMC (Electromagnetic Compatibility) regulations so you can sell it without affecting someone’s pacemaker? Unfortunately, a consequence of improved integrated circuit technology is that they are much more complicated, switch much faster, and use many different voltage levels. So it is not just a case of choosing your microcontroller and then connecting inputs to outputs. We have to worry about the parasitic components not shown on the schematic.

We also need to understand the advanced peripherals of modern microcontrollers and consider voltage levels, timing requirements, and how to lay out a printed circuit board to make them work reliably. Once upon a time, there was digital electronics and there was analogue electronics. But, somewhere along the line, the distinction got blurred. While digital signals have two states, in practice, they need to be treated as analogue signals. This is the focus of these lectures.

Lecture Contents

• 0 Introduction
• 1 Microcontrollers
• 2 Assignment
• 3 I/O Ports
• 4 Inverters
• 5 CMOS Inputs
• 6 CMOS Outputs
• 7 Logic Levels
• 8 CMOS Switching
• 9 Common Path Noise
• 10 Power Supply Decoupling
• 11 Power Supply Decoupling II
• 12 Crosstalk
• 13 Printed Circuit Boards
• 14 Transmission Lines
• 15 Transmission Line Reflections
• 16 Transmission Line Termination
• 17 Differential Signals
• 18 Clock Generation
• 19 IV Curves Supplement
• 20 CMOS Supplement
• 21 Transmission Line Supplement

Key Topics in High-Speed Design

• PIO ports: Most MCU pins are input/output ports (PIO) a.k.a. GPIO. This lecture describes how they work. There are some gnarly aspects if we want to minimize power consumption or avoid blowing things up on power-up.
• The CMOS inverter: PIO pins on MCUs are internally connected to CMOS inverters. Understanding the CMOS inverter is important when interfacing with PIO pins.
• CMOS inputs: CMOS has a high impedance and is thus susceptible to electrostatic discharge (ESD). Manufacturers add protection diodes, but these can lead to unexpected behavior.
• CMOS outputs: Conceptually, the CMOS inverter is just two switches, but these switches have nonlinear behavior.
• Logic levels: Here we look at noise margins and how to deal with logic running on different voltages.
• Logic switching: Modern logic devices switch rapidly, and we find that we need better I/O models to deal with parasitic components.
• Common path noise: In which we find that pesky parasitic inductance gets in the way of fast-changing signals.
• Power supply decoupling: Here capacitors come to the rescue to deal with the pesky inductance, but we find that capacitors are far from ideal.
• Crosstalk: This is where those parasitic circuit components not shown on the schematic cause signals to interfere with each other.
• PCB stackup: In which we look at how a multilayer PCB is constructed and how we use the different layers wisely.
• Transmission lines: Wires are far from ideal, and signals take time to propagate (even short distances across a PCB).
• Transmission line reflections: Here we consider what happens when we do not correctly terminate a transmission line.
• Differential signals: When we want super-fast signals, we use differential signaling. This helps to cancel crosstalk.
• Clock generation: Microprocessors all need a clock. Phase-locked loops (PLLs) come to the rescue since they can multiply the frequency of a clock.

Microcontrollers and Packaging

Billions of microcontrollers (MCUs) are sold each year. There are dozens of main manufacturers producing a wide variety from low-performance 8-bit microcontrollers to powerful 64-bit systems on chip (SOC).

Integrated Circuit Packaging

• Quad Flat Pack (QFP): This package is popular for prototyping since the pins can be hand-soldered. At a pinch, the pins can be probed with a scope. It is better to provide test points.
• Quad Flat No-Leads (QFN): These are difficult to hand-solder. However, they have a smaller package and smaller lead inductance.
• Ball Grid Array (BGA): This provides the highest pin density and smallest lead inductance with a matrix of solder blobs on the bottom. These packages are difficult for prototyping since the pins cannot be probed with a scope or unsoldered. X-ray imaging is required to determine if the pins are properly soldered.

MCU Pins and Power Supplies

Most MCU pins are input/output pins called PIO or GPIO. These are shared with peripheral signals (e.g., SPI, PWM, I2C, ADC, etc.). The second largest category are power supply pins. Finally, there are miscellaneous pins for programming/debugging, clocks, and reset.

Whenever a digital signal switches high, some capacitance needs to be charged. If a capacitance C is charged to a voltage V, then the energy stored in the capacitor is E = 0.5CV². However, in the process of charging, an equivalent amount of energy is dissipated in the resistance of the driving transistors. When the digital signal switches low, the same amount of energy is dissipated in the driving transistors when discharging the capacitance. Thus, if the signal switches at a frequency f, the power dissipated is P = fCV².

To minimize power dissipation and to ensure a good noise margin for external signals, it is common to have two or more power supply connections:

• VDDCORE: To power all the internal logic: CPU, peripherals, memory, etc.
• VDDIO: To power all the I/O pin drivers.

Power Supply Naming Conventions

• VDD: Voltage to drains; positive supply for CMOS (and NMOS) circuits.
• VSS: Voltage to sources; ground connection for CMOS circuits.
• VCC: Voltage to collectors; positive supply for BJT circuits.
• VKK: Voltage to cathodes (for valves/tubes).

I/O Ports and PIO Operation

To save pins and to provide greater flexibility, most microcontrollers use software-configurable bidirectional parallel input/output (I/O) ports. These are often called PIO (parallel I/O ports) or GPIO (general purpose I/O) ports.

PIO Pin Buffers

If you follow a bond wire connecting a PIO pin to the silicon die, you will get to a pair of buffers. One of these buffers is an input buffer; the other is an output buffer. The output buffer is a tri-state buffer with an enable pin to disable the output. The output state is held by a flip-flop and the data direction state is held by another flip-flop. On reset, the data-direction flip-flop is reset so the output buffer is disabled.

PIO Input and Metastability

The input buffer is typically a Schmitt trigger. This has hysteresis to reduce switching jitter for slowly changing input signals around the CMOS midpoint voltage. It is then connected to a chain of flip-flops to reduce the chances of metastability. Note, these flip-flops are clocked, and thus the input state cannot be read if this clock is stopped.

Metastability in a digital system is a temporary unstable state other than logic 0 or logic 1. It can occur when the input to a flip-flop is not stable for the required setup time before the flip-flop is clocked. Metastability is unavoidable whenever there are asynchronous inputs. However, by using a chain of synchronizing flip-flops, the probability that the last flip-flop is in a metastable state can be reduced to negligible levels.

Multifunction PIOs

One of the most limited resources on a microcontroller is the number of pins for input/output. Thus, microcontrollers share the PIO pins with peripherals using pin multiplexers (pin muxes) that can be configured by software. This allows the designer to route a peripheral output to multiple PIOs and simplify a PCB layout.

CMOS Inverters and Logic Behavior

Most digital integrated circuit inputs and outputs are connected to CMOS (Complementary Metal Oxide Semiconductor) inverters. The ideal inverter transfer function produces a high output for voltages below the switching (midpoint) voltage and a low output for voltages above it.

The CMOS Inverter Structure

The CMOS inverter consists of two MOSFET transistors in a totem-pole arrangement. The bottom transistor is N-type (NMOS) and the top transistor is P-type (PMOS). The drains are connected together and provide the output voltage. The advantage of the CMOS inverter over the NMOS inverter is that there is no static power loss and a large current can be sourced for fast switching high.

Power Consumption and Amplification

CMOS power dissipation is dominated by the charging/discharging of load capacitances: P = CV²f. CMOS inverters can also be used as analogue amplifiers by connecting a feedback resistor (typically 1–10 MΩ) between the input and output. The highest gain occurs when the input signals are biased around the switching voltage. Since a CMOS inverter has gain, it can be configured as an oscillator, such as the Pierce oscillator used for MCU clocks.

CMOS Inputs and ESD Protection

The input resistance of a CMOS device is extremely high, on the order of TΩ (10¹² Ω), in parallel with a small capacitance (typically 3–5 pF). This makes CMOS devices susceptible to electrostatic discharge (ESD) damage. To protect CMOS devices during handling, manufacturers include protection circuits, usually a pair of clamping diodes for each signal pin.

CMOS Back Drive

A CMOS device can be inadvertently powered by one of its signal lines. If a device is not powered by its VDD pin, its upper ESD clamping diode may conduct if the input voltage is greater than the voltage on its VDD pin. This provides power to the internal circuitry, which can lead to unexpected behavior or prevent a system from resetting properly.

CMOS Outputs and DC Loading

The output voltage of a CMOS device, and thus the noise margins, depends on the resistive loading. CMOS outputs have a totem-pole driver comprised of a PMOS pull-up transistor and an NMOS pull-down transistor. There are three modes of operation: output high (sourcing current), output low (sinking current), and high-impedance (tri-state).

Open-Drain Outputs

Open-drain (open-collector) outputs do not use the totem-pole configuration; they only have a pull-down transistor. A high output requires an external pull-up resistor connected to VDD. This simplifies interfacing to higher voltage logic levels or when multiple outputs share the same signal, such as in I2C or CAN buses. Open-drain outputs have a static power loss in the low state and are slower when switching from low to high.

Logic Levels and Noise Margins

When different ICs are interconnected, it is important for the logic levels to be compatible. Key parameters include Voh min, Vol max, Vih min, and Vil max. Digital signals are analogue signals contaminated by noise. The amount of noise a system can tolerate depends on the logic level noise margins:

• Logic high noise margin: Voh min - Vih min
• Logic low noise margin: Vil max - Vol max

A rule of thumb is that noise margins should be at least 0.2 V. If logic high and low output levels exceed the maximum voltages for the input device, latch-up can occur. Latch-up is a condition where a parasitic structure within the IC is triggered, causing the device to draw excessive current and potentially overheat.

CMOS Switching and Signal Bandwidth

The switching speed depends on how much current the driver can source (or sink) and the total load capacitance. The bandwidth of a signal is inversely proportional to the rise/fall times. One measure of the signal bandwidth is the knee frequency, commonly defined as fknee = 0.5 / t10-90%. High-frequency analysis of a logic device requires a model of the parasitic components, often provided in an IBIS (I/O Buffer Information Specification) model.

Common Path Noise and Ground Bounce

Common path noise results from switching currents flowing through the impedance of shared power supply connections. At high frequencies, the impedance of wires and traces is dominated by inductance. Even small inductances can induce large noise voltages: v(t) = L di/dt.

Ground bounce (and power bounce) occurs whenever the device output switches and discharges the load capacitance. The changing current induces a voltage across the lead inductance. This modulates the voltage reference used to make an input logic level decision. To mitigate this, use packages with short pins (BGA, QFN), multiple power/ground pins, and decoupling capacitors.

Power Supply Decoupling

Decoupling reduces both radiated and conducted electromagnetic interference (EMI) and improves signal integrity. Bypass (decoupling) capacitors provide a low-impedance path between power and ground. There are three levels:

1. Bulk bypass capacitors: For low-frequency decoupling, placed at the star point.
2. Local bypass capacitors: Placed as close as possible to the IC VDD and VSS pins to minimize loop area.
3. Interplane capacitance: For very high-frequency decoupling, achieved by closely spaced power and ground planes in a multilayer PCB.

MLCC (Multilayer Ceramic Chip) capacitors are preferred due to their low ESR and ESL. However, capacitors look inductive at high frequencies. Above 50 MHz, surface mount packages are required to remain effective.

Crosstalk and Signal Interference

Crosstalk is unwanted signals induced in victim traces from an aggressor trace due to mutual capacitance and mutual inductance. It is reduced by keeping loops small and far apart. The most practical ways to control crosstalk on a PCB are:

• Run traces over continuous planes to form microstrips.
• Do not run traces over gaps or splits in planes.
• Increase separation between traces (the 3-W rule).
• Slow down signal rise/fall times using series resistors.

Printed Circuit Boards (PCBs)

The PCB is the most critical component in a high-speed system. A multilayer PCB is a stack of alternating layers of prepreg mats and laminate sheets (cores). Every high-speed signal trace should be routed over a continuous plane to reduce loop area and control impedance. Every power supply should form a parallel power-ground plane capacitor for high-speed decoupling.

Transmission Lines and Reflections

If the propagation delay T is longer than 1/6 of a signal transition time, transmission line effects cannot be ignored. The characteristic impedance (Z0) relates the voltage to current of a propagating wave. If the load impedance is different from Z0, a reflection occurs. The voltage reflection coefficient is Γl = (Rl - Z0) / (Rl + Z0). Reflections can cause false clocking, timing jitter, and degraded EMC.

Termination Methods

• Parallel termination: A resistor to ground or VDD at the receiver.
• Thévenin termination: A resistor divider at the receiver.
• Series (source) termination: A resistor in series with the driver. This is common in CMOS systems as it has no static power loss.
• AC termination: A resistor and capacitor in series to ground.

Differential Signals

Modern high-speed buses (USB, Ethernet, PCI Express) use differential signals. Advantages include immunity to common-mode interference, tolerance of ground offsets, and better noise immunity. Differential signals need to be closely separated with constant geometry to ensure constant characteristic impedance and good EMC. Path lengths must be balanced to avoid timing skew.

Clock Generation and PLLs

Microcontrollers require a clock for timing. Quartz crystals are used for frequency stability due to their high Q factor. A Pierce oscillator is the standard circuit for MCU clocks. Phase-locked loops (PLLs) are used to multiply the crystal frequency to the required high-speed clock frequency. Some systems use spread-spectrum clocking to reduce spectral peaks and meet EMC requirements.

Exercises and Supplements

1. What are most of the pins on an MCU used for?
2. Why do many MCUs have multiple power supply pins of different voltages?
3. What is a PLL and what is it used for?
4. When a microcontroller first powers up, what state are the PIO pins?
5. Why should a PIO pin used as an input have a series resistor during development?
6. How can a CMOS inverter be configured as an amplifier?
7. Why is it undesirable to drive 3.3 V CMOS logic from 5 V CMOS logic?
8. What is the primary cause of switching noise in a high-speed digital circuit?
9. Why should power supply traces on a high-speed digital PCB be as wide as possible?
10. What is the point of local decoupling?