Operating System Memory Management: Paging and Segmentation

Page Fault Handling

• Hardware triggers the trap and saves the Program Counter (PC).
• The trap handler (interrupt routine) saves the registers.
• The OS detects a page fault.
• The OS searches for a free page frame. If none are available, it selects a victim page and evicts it.
• The OS initiates I/O for the page that triggered the fault.
• Once the disk interrupt handler notifies that the page has arrived, the process is scheduled for execution again.

Page Table Management

During each context switch, the current page table must be saved in the Process Control Block (PCB) and the new process's table must be loaded. Tables can be stored in:

Registers

• Provides faster access.
• If there is significant RAM, the table will have too many entries to fit in registers.
• Every context switch requires updating the value of all registers.

Memory

• A register points to the page table location.
• Slower than registers: requires two memory accesses per real access.
• No space limitations.
• During a context switch, only the register pointing to the table needs to be updated. All process tables remain in memory.

Additional Page Table Data

• Present bit: Indicates if the page is in RAM or swap.
• User/Kernel bit: Defines access permissions for user mode.
• Executable/Data bit: Indicates if the information is executable.
• OS metadata: Reference counters, access bits, etc.

These fields are defined by the hardware. The CPU operates with logical addresses rather than physical ones. Cache memory is implemented using logical addresses, and the Memory Management Unit (MMU) utilizes a Translation Lookaside Buffer (TLB) to accelerate address translation.

Translation Lookaside Buffer (TLB)

To reduce memory access time, systems use paging with tables stored in memory. The TLB is an associative memory that stores the N most recent logical-to-physical address translations, typically containing between 2 and 2048 entries.

Paging allows for efficient memory sharing between processes by pointing to the same physical frame from different page tables, improving memory usage and program execution speed.

Paging vs. Segmentation

• Compiler Awareness: In paging, compilers do not need to know if the system uses paging, as they always create a continuous logical address. In segmentation, compilers must generate addresses using different segments.
• Storage: Like paging, segment tables can be stored in registers or memory. If stored in memory, a special register indicates the base address of the segment table.
• Memory Division: Segmentation allows for logical division of memory, making it easier to define and share text segments between programs. This is more complex in pure paging.
• Physical Allocation: Unlike paging, each segment occupies a contiguous block of physical memory, and segments are of variable length.