I is correct ii is correct

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1. Number Systems & Data Types

Question 1: What is the decimal equivalent of 0xBEEF?

48879

Question 2: What is the decimal number equivalent of the octal value 0465?

Question 3: What is the binary equivalent of decimal 135?

0b10000111

Question 4: What is the octal equivalent of 0x5EED?

057355

Question 5: What is the binary equivalent of 0xBEAD?

0b1011111010101101

Question 6: What is the range of an unsigned byte?

0 to 255

Question 7: What is the range of a signed word?

0x80000000 to 0x7FFFFFFF

[Exam 1] Question 8: What is the two's complement representation of -128 expressed as a signed half word?

0b1111111110000000

[Exam 1] Question 9: What is the Octal equivalent of Hex 0xDEAF?

0157257

[Exam 1] Question 10: Convert 0xA1A to decimal:

2586

[Exam 1] Question 11: What is the correct binary representation of decimal 520?

0b1000001000

[Exam 1] Question 12: The decimal value of the Octal number 0750 is...

[Exam 1] Question 13: Place the maximum and minimum values of each data type in the correct categories.

Unsigned Byte: 0x00, 0xFF, +255
Signed Byte: 0x80, -128, 0x7F, +127
Unsigned Halfword: 0x0000, 0xFFFF, +65,535
Signed Halfword: 0x8000, -32,768, 0x7FFF, +32,767
Unsigned Word: 0x00000000, 0xFFFFFFFF, +4,294,967,295
Signed Word: 0x80000000, -2,147,483,648, 0x7FFFFFFF, +2,147,483,647

[Exam 2] Question 14: A floating point variable includes which of the following?

Sign, Exponent, Mantissa

🌟 Concept Expansion: Number Systems & Floating Point
1's vs 2's Complement: 2's Complement is found by inverting all bits of the positive binary number and adding 1.
Sign Extension: To make an 8-bit negative number (-128) into a 16-bit negative number, pad the left side with 1s (the sign bit). This preserves the negative value.
IEEE 754 Floating Point: Consists of 3 parts:
Sign bit: 1 bit (0 for positive, 1 for negative).
Exponent: 8 bits (for single precision), shifted by a bias.
Mantissa (or Fraction): 23 bits representing the significant digits.

2. Computer Architecture and Memory

Question 1: Match each register to its description / function. (Combined)

IR: Holds the current instruction being processed by the microprocessor
MAR: Contains the address in memory that is to be read from or written to
MDR: Stores data that is read from memory or to be written to memory
SP: Points to memory location of the last item placed on the stack
GENERAL PURPOSE (R0-R12): Used to hold data values inside the processor for use in instructions (connected to the ALU)
PSR: Contains processor status flags (NZCVQ)
PC: Contains the address of the instruction that will execute next
LR: Address of the instruction to be executed after returning from a subroutine
CONTROL: Used to configure features of the processor

Question 2: Place the registers in their appropriate categories

General Purpose: r5, r12, r2, r0
Special Purpose: PC, SP, PSR, LR
Special Purpose but not User Accessible: MAR, IR, MDR
Uncategorized: NOR, AND, DUD

Question 3: True or False - ROM is typically faster than RAM

False

[Exam 1] Question 4: True or False - Big Endian is where the least significant byte is stored at the lowest memory address...

False (That describes Little Endian).

Question 5: What are the properties of general purpose and special purpose computers?

General Purpose: Speed and cost are critical parameters, End-user programmable, Designed to execute any program, Contains a microprocessor.
Special Purpose: Fixed run-time constraints for power consumption/size/cost, Designed to perform one or just a few tasks, Contains a microcontroller, Not end-user programmable.

Question 6: Group the features of these two architectures.

Von Neumann: Single address space for instructions and data, Can only fetch one instruction at a time, Must complete each instruction before starting the next.
Harvard: Separate address spaces for instructions and data, Can simultaneously read an instruction while reading or writing data. [Exam 1]: True - Harvard is typically faster because it allows simultaneous access.

Question 7: What are the properties of RISC and CISC processors?

RISC: Complexity resides in the compiler, Simple instructions, Small number of instructions (30-40), One instruction per clock cycle, Multiple generic data registers, Instructions are pipelined, Simple addressing modes, Load and Store addressing.
CISC: Complexity resides in the CPU, Multiple clock cycles per instruction, Unique registers, Large number of instructions (100-300), Complex addressing modes, Instructions execute sequentially, Set based addressing, Complex instructions.

Question 8: Match each section of program memory with its proper description.

.Text: Program code
.Rodata: Constants
.Data: Initialized variables ([Exam 1]: This defines the start of the initialized variable space).
.Bss: Uninitialized global and static variables

Question 9: Match the answers to the questions.

ADDRESS BUS: Used to select a specific address in memory to read or write data
DATA BUS: Used to send or receive data to and from memory
BUS: A set of parallel wires that transmit binary information
CONTROL LINES: Used to control behavior (like read/write)
CPU: A state machine that executes program instructions

3. Toolchains, Compilation, and CPU Execution

Question 1: Identify the function of each part of the toolchain.

Compiler: Converts high level code to assembly (.C to .S)
Assembler: Converts assembly code to machine code (.S to .O)
Linker: Combines object files to create a complete program executable
Preprocessor: Prepares high level code to be compiled and generates the symbol table
objcopy: Converts an executable to a binary image file for loading into hardware
objdump: Disassembles machine code to assembly for an executable

[Exam 1] Question 2: Which of the following are part of the software toolchain?

Compiler, Linker, Assembler

Question 3: What is the proper order of the steps in compiling a program?

Preprocessing
Compilation
Assembly
Linking
Object Copy
Device Programming

Question 4: Put the instruction execution steps in the proper order.

Instruction Fetch
Instruction Decode
Operand Fetch
Execution
Results Storage
Increment Program Counter

Question 5: Pipelining Characteristics * [Quiz]: An advantage of pipelining is it increases throughput to achieve one instruction per clock cycle.

[Exam 1]: Pipelining is a processing technique that allows simultaneous execution of stages of instructions to maximize processor throughput.

4. ARM Assembly Language & Instructions Sets

Question 1: Place the statements in the correct categories

Accumulator Instruction Set: Dedicated Accumulator Register, ALU results always goes in the accumulator, Used in simple processors.
Stack Based Instruction Set: ALU operands and results are stored on the stack, Common to older mainframe computers.
Load/Store Instruction Set: ALU can source data from any general purpose register, Data must be loaded from memory into registers, ALU can store results in any register, Data must be stored from registers into memory.

Question 2: Match each instruction to the proper addressing mode (Combined)

Register Indirect: LDR r0, [r1]
Register Indirect with register offset: LDR r0, [r1, r2]
Pre-Indexed: LDR r0, [r1, #4]!
Post-Indexed: LDR r0, [r1], #8
Immediate: LDR r0, #0x25
Implied: PUSH {LR}

[Exam 1] Question 3: Identify the parts of the following instruction: math: add r4, r2, r1

math:: label | add: mnemonic | r4: destination/operand1 | r2: source/operand2 | r1: source/operand3

Question 4: Place each instruction in its proper category. (Combined)

Data Transfer: LDR, STR, MOV, LDRB, ADR, PUSH
Data Manipulation: REV, ASR, MUL, AND, SUB, LSR, DIV, RBIT, ADD, BIC, EOR
Program Control: BX, BL, B, BEQ, CBZ

Question 5: Functional Equivalence.

[Exam 1]: True - ADR r4, b is functionally equivalent to LDR r4, =b.
[Quiz]: True - In order to place an immediate value larger than a byte into a register, you must use LDR r0, =0x12345678 instead of MOV r0, #0x12345678.

Question 6: Which instruction would you use to load a signed byte of data from memory into register r0?

LDRSB r0, [r4]

Question 7: Which Cortex family is used for embedded computing?

Cortex-M Series

Question 8: ___ is a newer version of the ARM instruction set that combines both 16 bit and 32 bit instructions.

Thumb-2

[Exam 1] Question 9: What function does this code perform?

z = 8*a + b - 6

[Exam 1] Question 10: Place the assembly instructions in the correct order to do this function: for (i = 5; i > 0; i--) x = x*2;

mov r1, #5
loop:
mov r0, r0, lsl #1
subs r1, r1, #1
bnz loop

[Exam 1] Question 11: True or False - In the following code, after returning from sub2: the program will return from sub1: back to the main loop. (Referencing nested bl without PUSHing LR)

False (Because bl overwrites the Link Register).

5. Flags, Bitwise Logic, and Barrel Shifter Math

Question 1: Match the flag with the description.

N: Result of operation is negative
Z: Result of the operation is zero
C: The operation resulted in a carry
V: The operation resulted in an overflow
Q: Result of the operation was saturated

Question 2: Flag Conditions for Branches / Operations

CBZ: Uses Z flag.
BEQ: Branches when Z = 1, N = 0.
MI and PL: Use the N flag.
CMP r0, r1: Performs r0 - r1 to set the flags.
[Quiz] True/False: An ALU operation must have an S appended to the instruction in order for flags to be updated. (True)

Question 3: True or False - Logical Flag Setting

[Exam 1]: MOV R0, #0x55 | MOV R1, #0xAA | TEQ R0, R1. Z flag is set to 1? (False - TEQ is XOR, result is not zero).
[Exam 1]: MOV R0, #0x55 | MOV R1, #0xAA | TST R0, R1. Z flag is set to 1? (True - TST is AND, result is zero).

Question 4: Match each logical operation with the bit manipulation function it can perform.

AND: Pass selected bits using a mask
ORR: Set selected bits using a mask
BIC: Clear selected bits to 0 using a mask
EOR: Flip selected bits using a mask
MVN: Flip every bit of a word

[Exam 2] Question 5: The digits 0 through 9 have ASCII hex values of 0x30 to 0x39. If you want to extract the numeric value, which line of code do you use?

Value = Character & 0xF;

Question 6: Barrel Shifter Properties

[Quiz]: Reduces instruction memory usage and allows for a shift and another operation to occur on a single clock cycle.
[Exam 1]: True/False - The barrel shifter is part of the ALU that can act on the second source operand. (True).
[Exam 1]: True/False - ADDS R1, R2, R3, LSL #3 flag status is determined by the shift operation, not the add operation. (False).

Question 7: Shifting for Multiplication and Division

[Quiz]: To divide a signed integer by a power of 2, use ASR.
[Quiz]: To multiply by 16: LSL R0, #4.
[Exam 1]: To do a signed divide by 32: ASR R0, #5.

Question 8: Execution Results (Logic and Math)

MOV R1, #0x35, MOV R2, #0xF0, AND R0, R1, R2 -> 0x30
MOV R1, #0x35, MOV R2, #0xF0, EOR R0, R1, R2 -> 0xC5
mov r0, #0x35, mov r1, #0x3C, and r2, r0, r1 -> 0x00000034
mov r0, #0x35, mov r1, #0x3C, eor r2, r0, r1 -> 0x00000009
ldr r0,=0x34560701, ldr r1,=0x56745670, and r2, r0, r1 -> 0x14540600
ldr r0,=0x34560701, ldr r1,=0x56745670, eor r2, r0, r1 -> 0x62225171
ldr r0,=0x34560701, ldr r1,=0x56745670, add r2, r0, r1 -> 0x8ACA5D71

Question 9: Execution Results (Bitfield and Extensions)

ldr r0,=0x12345678, bfc r0, #16, #8 -> 0x12005678
ldr r0,=0x12345678, ldr r1,=0xFFFFFFFF, bfi r1, r0, #8, #16 -> 0xFF5678FF
ldr r0,=0x12345678, ldr r1,=0x00000000, sbfx r1, r0, #16, #16 -> 0x00001234
ldr r0,=0x85, ldr r1,=0x00000000, sxtb r1, r0 -> 0xFFFFFF85
ldr r0, =0x08000000, SSAT r1, #16, r0, USAT r2, #16, r0 -> r1 = 0x00007FFF and r2 = 0x0000FFFF

Question 10: Match each instruction with its function.

REV: Reverse the byte order of a 32-bit word.
REV16: Reverse the byte order of each half word in a 32-bit word.
REVSH: Reverse the byte order of the lower half word in a 32-bit word and sign extend the result.
RBIT: Reverse the bit order of a 32-bit word.

6. C Language

Question 1: C Formatting and Syntax Rules

[Quiz]: All variables must be declared with their data types before they can be used. Every C statement must end with a semicolon. Every C program must have one main function.
[Exam 2]: All variables must be declared with their data type before they can be used. (True)
[Exam 2]: C has strict formatting rules for how code is placed within the program text, including alignment and white space count. (False - C ignores whitespace).
[Exam 2]: What symbols are used to enclose multiple line comments? /* and */

Question 2: Keywords and Operators

[Quiz]: Valid keywords: if, signed.
[Exam 2]: NOT a keyword: not.
[Exam 2]: Which symbol is not correct for use in an if statement comparison? = (Assignment).
[Exam 2]: Match the operators:
- Assignment: = += -= *= &= |=
- Bitwise: & | ^ ~ << >>
- Relational: > < >= <= == !=
- Logical: || && !
- Arithmetic: + - / * % ++ --

[Exam 2] Question 3: Variable and Array Declarations

Invalid declaration: int Fast-Car; (Hyphens are illegal).
Invalid declaration: int register; (register is a reserved keyword).
Invalid array declaration: arr[ ][ ] = { {1,2} , {3,4} , {5,6} }; (Multidimensional arrays must specify inner bounds).
int turtles[5][8]; Illegal instruction: turtles[3][8] = 2; (Index out of bounds, max is 7).

[Exam 2] Question 4: Pointers and Directives

Which statement declares Point as a pointer? int *Point;
To link in another file, use: #include.
Which compiler directive can be used with #if #elif to conditionally compile code? #define.

Question 5: C Math and Casting Execution

[Quiz]: int X[5][2] = { {0,0}, {1,2}, {2,4}, {3,6}, {4,8} }; Y = X[2][1]; -> 4
[Exam 2]: t = 4; x = t++; y = --t; What are the values of x, y? -> 4, 4
[Exam 2]: short X = 0x4507; char Y = (char) X; What value does Y contain? -> 7

🌟 Concept Expansion: Pointers and Operators
Pre-increment vs Post-increment: x = t++ (Post-increment) evaluates t and assigns it to x, then increments t. x = ++t (Pre-increment) increments t first, then assigns the new value to x.
Casting: Downcasting from a 16-bit short (0x4507) to an 8-bit char truncates the upper bits. 0x4507 becomes 0x07 (Decimal 7).
Pointers: A pointer stores the memory address of another variable. Declared with * (e.G., int *ptr). The address of a variable is fetched with & (e.G., ptr = &var).

Question 6: Data Types and Scopes

[Exam 2]: How many bytes does a char data type use on the ARM M4 processor? -> 1
[Quiz]: How many bytes does a standard int contain on the M4 ARM processor? -> 4
[Exam 2]: Which storage class makes a local variable visible globally? -> extern
[Quiz]: True or False - By default, local variables maintain their values throughout the life of the program. -> False

7. GPIO, Device Interfaces, Interrupts, ADC and DAC

Question 1: Enums and GPIO Ports

enum colors {red, green, blue, yellow, cyan, magenta}; Value of yellow? -> 3. Value of magenta? -> 5.
portA |= (analog << (pin4*2)) | output << (pin1*2); -> 0x0304
[Exam 2]: portA |= (analog << (pin3*2)) | output << (pin2*2); -> 0x000000D0

Question 2: What is the function of each GPIO register? (Combined)

OTYPER: Register for setting push-pull or open drain modes for digital outputs
MODER: Register for setting the mode for each pin
IDR: Input data register
ODR: Output data register
PUPDR: Pull-up, pull-down register for digital inputs

Question 3: Match the bit manipulation operation with the description (ODR Modification) (Combined)

GPIOD->ODR |= 1<<n;: Set bit n to 1
GPIOD->ODR &= ~(1<<n);: Set bit n to 0
GPIOD->ODR ^= 1<<n;: Invert bit n
GPIOD->ODR &= 1<<n;: Set all bits to 0 but leave bit n unchanged
GPIOD->ODR |= ~(1<<n);: Set all bits to 1 but leave bit n unchanged

[Exam 2] Question 4: When an I/O pin is defined to work as an open drain output pin, the outputs that can be driven by the pin in this case are?

Undriven / Ground

[Exam 2] Question 5: What type of resistor is R1? (Tied between the pin and VDD/Supply)

pull-up

🌟 Concept Expansion: GPIO Output Modes
Push-Pull: The microcontroller can actively drive the pin HIGH (VDD) or LOW (Ground) using internal transistors.
Open Drain: The microcontroller can only pull the pin LOW (Ground). When set to HIGH, it simply disconnects (Undriven/High-Z). An external pull-up resistor is required to bring the voltage up to HIGH. This is used safely link devices operating at different voltage levels (like I2C).

[Exam 2] Question 6: Categorization of C instructions (A/D converter and LED array)

Initialize all clocks: RCC->APB2ENR |= 1<<8; // ADC1, RCC->AHB1ENR |= 1<<3; // Port D, RCC->AHB1ENR |= 1; // Port A
Initialize all hardware: GPIOD->MODER = 0x55555555; // All pins outputs, GPIOA->MODER = 0x0000000FF; // Pot 1, ADC1->CR2 |= 1; // Enable ADC1, ADC1->SQR3 = 1; // Pot 1
If statement and code that goes inside the if statement { }: ADC1->CR2 |= 1<<30; // Start conversion, If ((ADC1->SR & 1<<1) > 0), GPIOD->ODR = ADC1->DR;

Question 7: Interrupts (IRQ vs ISR) (Combined)

IRQ: Hardware or Software, Interrupt Request, Internal or External, Has a number between -15 and +240, Maskable or Non-Maskable.
ISR: Interrupt Service Routine, Handles Interrupts, Pointed to by the Vector Table, Has a procedure name defined.

Question 8: Interrupt Handling specifics

[Quiz]: Which hardware block manages interrupts in the STM32F407? -> NVIC
[Exam 2]: Where does the processor find the address of the ISR? -> Vector Table
[Exam 2]: When an interrupt occurs, it is handled by? -> Interrupt Service Routine
[Exam 2]: An interrupt can be prevented from interrupting the normal program execution by using? -> Masking
[Quiz]: Which registers are automatically pushed onto the stack when an ISR is called? -> PSR, LR, SP, R12, R0-R3, PC.

Question 9: ADC Specs

What determines the sampling resolution of the ADC? -> Number of bits
How many bits of resolution does the ADC used in the STM32F407 have? -> 12
[Exam 2]: The process of capturing an analog voltage and storing it on a capacitor in an A/D converter is called? -> Sample and hold
[Exam 2]: The dude that says the sampling rate must be at least twice the highest frequency content of a signal is named? -> Nyquist

Question 10: DAC Specs

What type of DAC is used in the STM32F407? -> R2R
[Exam 2]: True or False - The R2R DAC is less susceptible to process variations in the semiconductor fabrication process. -> True
DAC Specifications: Linearity, Resolution, Settling Time, Speed, Reference Voltage
DAC Error Types: Gain, Full-Scale, Offset, Non-linearity, Non-monotonic, LSB

8. Timers and PWM, Motors, Serial Communications

Question 1: Timers

Which of the following are functions that Timers can perform: Provide periodic interrupts, Generate PWM outputs.
Which timer register contains the value that resets the counter to zero when the timer counter matches it? -> ARR
The parameter that divides the clock frequency down for the timer is called the -> prescaler

Question 2: PWM and Motors

? = 100 * Ton / (Ton + Toff ). Select the name of the parameter represented by the ? In the equation. -> % Duty Cycle
The circuit that allows the direction of a DC motor to be controlled is called? -> H-Bridge
PWM can be used to control the -> speed of a DC motor.
What is the frequency of the PWM signal used to control a servo motor? -> 50 Hz
The part of a servo motor that compares the output position voltage to the converted PWM voltage is called? -> Error Amplifier
Which type of motor is best for precise positioning of machinery? -> Stepper

Question 3: Serial Communications

UART (serial): Synchronous or Asynchronous, Optional Parity bit, Speed set by Baud Rate, Full-Duplex, One Start bit and One or Two Stop Bits.
I2C: Synchronous 2-wires, Has Master and Slave devices, supports multi-master, Half-Duplex with clock and data lines, Devices have addresses of 7-bits/10-bits/16-bits, external pull-up resistors are required.
SPI: Single Master, Synchronous 4-wires, Circular Data Transfer buffers, simultaneous transfer both directions, Protocol defined by slave device.
If the 8 data bits for a UART has an even number of 1's set, and the parity bit is set to a one, then the parity mode is -> odd parity.

9. Serial Communications and USB (Quiz 13)

Question 1: True or False - RS-232 is a signaling standard for level shifting logic level UART signals to higher differential voltages for longer distance communications. -> True

Question 2: Match the communications terms to their descriptions.

Simplex: Data flows one way from the transmitter to the receiver
Half Duplex: Data flows both ways in an alternating fashion sharing a single channel
Full Duplex: Data flows both ways simultaneously
Synchronous Signaling: A clock is used to time the transmission of data
Asynchronous Signaling: Data is transmitted without a clock and both the sender and receiver have to agree on the timing.
Serial / Parallel: Sent one bit at a time / Sent as multiple bits at the same time.
Ack/Nack: A signal from the receiver to indicate the success or failure of data transmission
Parity / CRC: Detects single bit errors / Computes most errors over an entire message.
Handshaking: The use of signals to establish a communications session
Baud: The number of symbols or characters per second
Frame: The complete bit pattern used to complete a single message from start to stop condition
Bus Arbitration: Method used to resolve conflicts between multiple masters sharing a bus
Clock Polarity/Phase: Two parameters used to define the clock characteristics for a SPI bus

Question 3: Match the USB terms with their definitions.

USB Versions: 1.0 (Low/Full Speed), 2.0 (High Speed, OTG), 3.0 (Super Speed, Type C).
Host / Peripheral: The master upstream device / The slave downstream device.
Bus Powered / Self Powered: Power from the Host / Power from a separate supply.
OTG (On The Go): Allowing devices to swap roles based on the state of the ID line in a cable.
Power Delivery: Negotiating the voltage and current used to power a device.
Transfers: Isochronous (guaranteed average rate, might lose data), Interrupt (guaranteed latency), Bulk (large data, uses remaining bandwidth).
Pipes and Endpoints: Pipe (virtual serial channel to a function), Endpoint (destination inside a peripheral).
Descriptors: Device (tells host what it is), Configuration (functional configuration), Interface (device class/number of endpoints), Endpoint (communications details).

10. Cache Memory (Week 14)

Question 1: Place the memory characteristics in the correct category.

SRAM: Typically KBytes to MBytes, Made with Flip Flops, Faster Access Time, Expensive, Static Memory.
DRAM: Made with MOSFETs and capacitors, Dynamic Memory, GBytes, Slower Access Time, Inexpensive.

Question 2: Place the memory types in order from fastest to slowest.

Registers
L1 Cache
L2 Cache
L3 Cache
DRAM
Solid State Drive
Hard Drive

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