Computer Architecture and Organization Fundamentals
Computer Architecture vs. Computer Organization
| Computer Architecture | Computer Organization |
|---|---|
| Deals with functional behavior | Deals with structural relationships |
| Visible to programmer (instruction set, addressing modes) | Invisible to programmer (control signals, memory technology) |
| Describes WHAT the system does | Describes HOW it is implemented |
| Example: x86 architecture | Example: Intel Core i7 vs. Pentium |
IEEE 754 Floating Point Bias
- Single Precision (32-bit): Bias = 127 (27 - 1)
- Double Precision (64-bit): Bias = 1023 (210 - 1)
Why Bias is Used
Bias allows storing both positive and negative exponents using only unsigned integers. Instead of storing the actual exponent, we store (exponent + bias), which is always positive. This simplifies the comparison of floating-point numbers.
Cache Memory Performance
Hit Ratio and Effective Access Time
Hit Ratio (h): The ratio of the number of successful cache accesses (hits) to total memory accesses.
h = Number of Hits / Total Accesses
Effective Access Time (EAT) Formula:
EAT = h × Tc + (1-h) × (Tc + Tm)
Simplified: EAT = Tc + (1-h) × Tm
Where: Tc = Cache access time, Tm = Main memory access time
Direct Memory Access (DMA)
DMA (Direct Memory Access): A technique that allows I/O devices to transfer data directly to or from memory without CPU involvement. The DMA controller takes control of the system bus and handles the transfer.
Three Modes of DMA Operation
- Burst Mode: DMA takes complete bus control until the entire transfer is done.
- Cycle Stealing Mode: DMA steals one bus cycle at a time, transferring one word per steal.
- Transparent Mode: DMA uses the bus only when the CPU is not using it.
Carry Look-ahead Adder (CLA)
In a Carry Look-ahead Adder:
- Generate (Gi) = Ai · Bi — Carry is generated when both inputs are 1.
- Propagate (Pi) = Ai ⊕ Bi — Carry is propagated when exactly one input is 1.
- Sum: Si = Pi ⊕ Ci
- Carry: Ci+1 = Gi + Pi · Ci
Booth's Algorithm Multiplication
Task: Multiply (-7) × (+5) using 5-bit representation.
Given: Multiplicand M = +5 = 00101, Multiplier Q = -7 = 11001 (2's complement)
Setup: -M = 11011, n = 5 bits
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