VHDL Implementations for Digital Logic Components
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VHDL Flip-Flop Implementations
This section demonstrates various VHDL implementations of flip-flops and latches, showcasing different clocking, clear, preset, and load mechanisms.
entity reginf is
port (
d, clk, clr, pre, load, data : in std_logic;
q1, q2, q3, q4, q5, q6, q7 : out std_logic
);
end reginf;
architecture rtl of reginf is
begin
Active High Clock D-Latch
A simple D-latch sensitive to the rising edge of the clock.
-- D-latch with active high clock
process
begin
wait until clk='1';
q1 <= d;
end process;
Active Low Clock D-Latch
A D-latch sensitive to the falling edge of the clock.
-- D-latch with active low clock
process
begin
wait until clk='0';... Continue reading "VHDL Implementations for Digital Logic Components" »