VHDL Implementations for Digital Logic Components
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VHDL Flip-Flop Implementations
This section demonstrates various VHDL implementations of flip-flops and latches, showcasing different clocking, clear, preset, and load mechanisms.
entity reginf is
port (
d, clk, clr, pre, load, data : in std_logic;
q1, q2, q3, q4, q5, q6, q7 : out std_logic
);
end reginf;
architecture rtl of reginf is
begin
Active High Clock D-Latch
A simple D-latch sensitive to the rising edge of the clock.
-- D-latch with active high clock
process
begin
wait until clk='1';
q1 <= d;
end process;
Active Low Clock D-Latch
A D-latch sensitive to the falling edge of the clock.
-- D-latch with active low clock
process
begin
wait until clk='0';
q2 <= d;
end process;
Active High Clock D-FF with Asynchronous Clear
A D flip-flop with an active high clock and an asynchronous clear input.
-- D flip-flop with active high clock and asynchronous clear
process (clk, clr)
begin
if clr = '1' then
q3 <= '0';
elsif clk'event and clk = '1' then
q3 <= d;
end if;
end process;
Active High Clock D-FF with Synchronous Clear
A D flip-flop with an active high clock and a synchronous clear input.
-- D flip-flop with active high clock and synchronous clear
process (clk, clr)
begin
if clk'event and clk = '1' then
if clr = '1' then
q4 <= '0';
else
q4 <= d;
end if;
end if;
end process;
Active High Clock D-FF with Asynchronous Load
A D flip-flop with an active high clock and an asynchronous load input.
-- D flip-flop with active high clock and asynchronous load
process (clk, load, data)
begin
if load = '1' then
q5 <= data;
elsif clk'event and clk = '1' then
q5 <= d;
end if;
end process;
Active High Clock D-FF with Synchronous Load
A D flip-flop with an active high clock and a synchronous load input.
-- D flip-flop with active high clock and synchronous load
process
begin
wait until clk'event and clk = '1';
if load = '1' then
q6 <= data;
else
q6 <= d;
end if;
end process;
Active High Clock D-FF with Async Clear & Preset
A D flip-flop with an active high clock, asynchronous clear, and asynchronous preset.
-- D flip-flop with active high clock, asynchronous clear and preset
process (clk, clr, pre)
begin
if clr = '1' then
q7 <= '0';
elsif pre = '1' then
q7 <= '1';
elsif clk'event and clk = '1' then
q7 <= d;
end if;
end process;
end rtl;
VHDL Sequence Detector for "1011"
This section presents a VHDL implementation of a finite state machine (FSM) designed to detect the sequence "1011".
library ieee;
use ieee.std_logic_1164.all;
entity detecta is
port (
e : in std_logic; -- Input bit
clk : in std_logic; -- Clock
reset : in std_logic; -- Asynchronous reset
s : out std_logic -- Output: '1' when sequence detected
);
end detecta;
architecture behavioral of detecta is
type state_type is (E0, E1, E2, E3, E4); -- E0: Initial, E1: '1', E2: '10', E3: '101', E4: '1011'
signal current_state, next_state : state_type;
signal s_next : std_logic;
begin
-- Synchronous process for state and output updates
sync_proc: process (clk)
begin
if rising_edge(clk) then
if reset = '1' then
current_state <= E0;
s <= '0';
else
current_state <= next_state;
s <= s_next;
end if;
end if;
end process sync_proc;
-- Next state decode logic
next_state_decode: process (current_state, e, reset)
begin
next_state <= current_state; -- Default to stay in current state
if reset = '1' then
next_state <= E0;
else
case current_state is
when E0 => -- Waiting for '1'
if e = '1' then
next_state <= E1;
else
next_state <= E0;
end if;
when E1 => -- Received '1', waiting for '0'
if e = '0' then
next_state <= E2;
else
next_state <= E1; -- Stay in E1 if another '1' comes
end if;
when E2 => -- Received '10', waiting for '1'
if e = '1' then
next_state <= E3;
else
next_state <= E0; -- Reset if '0' comes
end if;
when E3 => -- Received '101', waiting for '1'
if e = '1' then
next_state <= E4; -- Sequence '1011' detected
else
next_state <= E0; -- Reset if '0' comes
end if;
when E4 => -- Sequence '1011' detected, reset to initial state for non-overlapping detection
next_state <= E0;
end case;
end if;
end process next_state_decode;
-- Output decode logic
output_decode: process (current_state)
begin
s_next <= '0'; -- Default output
if current_state = E4 then
s_next <= '1'; -- Output '1' when the sequence '1011' is detected
end if;
end process output_decode;
end behavioral;
VHDL SRAM Model (Synchronous Write, Asynchronous Read)
This VHDL code models a Static Random Access Memory (SRAM) with a synchronous write operation and an asynchronous read operation. It includes generic parameters for address and data bus widths.
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all; -- For to_integer(unsigned(addr))
entity sram is
generic (
addr_width : integer := 8;
data_width : integer := 8
);
port (
clk : in std_logic; -- Clock for synchronous write
we : in std_logic; -- Write Enable
addr : in std_logic_vector(addr_width - 1 downto 0); -- Address input
din : in std_logic_vector(data_width - 1 downto 0); -- Data input for write
dout : out std_logic_vector(data_width - 1 downto 0) -- Data output for read
);
end sram;
architecture behavioral of sram is
-- Define the RAM type as an array of std_logic_vectors
type ram_type is array (2**addr_width - 1 downto 0) of std_logic_vector(data_width - 1 downto 0);
signal ram : ram_type;
begin
-- Synchronous write process
process (clk)
begin
if rising_edge(clk) then
if we = '1' then
ram(to_integer(unsigned(addr))) <= din; -- Write data to RAM
end if;
end if;
end process;
-- Asynchronous read: dout reflects content at 'addr' immediately
dout <= ram(to_integer(unsigned(addr)));
end behavioral;