VHDL Implementations for Digital Logic Circuits

VHDL Code Examples for Digital Logic Design

This document presents several VHDL code examples demonstrating the implementation of various digital logic circuits, including custom combinational functions and a priority encoder. These examples illustrate fundamental VHDL constructs for hardware description.

Custom Combinational Logic Function (EFC_17_F) - Decoder Label

This VHDL module, named EFC_17_F, implements a specific combinational logic function. In the original context, it was labeled as a "decoder." It takes four standard logic inputs (P1, P0, M1, M0) and produces a single standard logic output (C). The output C is asserted ('1') for specific input combinations, effectively acting as a custom boolean function.

LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;

ENTITY EFC_17_F IS
    PORT ( P1 : IN STD_LOGIC;
           P0 : IN STD_LOGIC;
           M1 : IN STD_LOGIC;
           M0 : IN STD_LOGIC;
           C  : OUT STD_LOGIC);
END EFC_17_F;

ARCHITECTURE A_EFC_17_F OF EFC_17_F IS
    SIGNAL ENTRADA: STD_LOGIC_VECTOR (3 DOWNTO 0);
BEGIN
    ENTRADA <= P1 & P0 & M1 & M0;
    WITH ENTRADA SELECT
        C <= '1' WHEN "0101" | "0110" | "1010" | "1011" | "1111",
             '0' WHEN OTHERS;
END A_EFC_17_F;

Custom Combinational Logic Function (EFC_17_F) - Multiplexer Label

This is an identical VHDL module to the previous one, also named EFC_17_F, but was originally labeled as a "multiplexer." Despite the differing labels, the code implements the same custom combinational logic function, taking four inputs and producing a single output based on specific input patterns.

LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;

ENTITY EFC_17_F IS
    PORT ( P1 : IN STD_LOGIC;
           P0 : IN STD_LOGIC;
           M1 : IN STD_LOGIC;
           M0 : IN STD_LOGIC;
           C  : OUT STD_LOGIC);
END EFC_17_F;

ARCHITECTURE A_EFC_17_F OF EFC_17_F IS
    SIGNAL ENTRADA: STD_LOGIC_VECTOR (3 DOWNTO 0);
BEGIN
    ENTRADA <= P1 & P0 & M1 & M0;
    WITH ENTRADA SELECT
        C <= '1' WHEN "0101" | "0110" | "1010" | "1011" | "1111",
             '0' WHEN OTHERS;
END A_EFC_17_F;

VHDL Priority Encoder (EFC_15_S)

The EFC_15_S entity represents a 7-input priority encoder. This circuit prioritizes its inputs, meaning if multiple inputs are active ('1'), the output corresponds to the highest-priority active input. It takes seven standard logic inputs (E1 through E7) and outputs a 3-bit binary code (S2, S1, S0) representing the highest active input.

LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;

ENTITY EFC_15_S IS
    PORT ( E1 : IN STD_LOGIC;
           E2 : IN STD_LOGIC;
           E3 : IN STD_LOGIC;
           E4 : IN STD_LOGIC;
           E5 : IN STD_LOGIC;
           E6 : IN STD_LOGIC;
           E7 : IN STD_LOGIC;
           S0 : OUT STD_LOGIC;
           S1 : OUT STD_LOGIC;
           S2 : OUT STD_LOGIC);
END EFC_15_S;

ARCHITECTURE A_EFC_15_S OF EFC_15_S IS
BEGIN
    PROCESS (E1, E2, E3, E4, E5, E6, E7)
    BEGIN
        IF E7 = '1' THEN S2 <= '1'; S1 <= '1'; S0 <= '1';
        ELSIF E6 = '1' THEN S2 <= '1'; S1 <= '1'; S0 <= '0';
        ELSIF E5 = '1' THEN S2 <= '1'; S1 <= '0'; S0 <= '1';
        ELSIF E4 = '1' THEN S2 <= '1'; S1 <= '0'; S0 <= '0';
        ELSIF E3 = '1' THEN S2 <= '0'; S1 <= '1'; S0 <= '1';
        ELSIF E2 = '1' THEN S2 <= '0'; S1 <= '1'; S0 <= '0';
        ELSIF E1 = '1' THEN S2 <= '0'; S1 <= '0'; S0 <= '1';
        ELSE S2 <= '0'; S1 <= '0'; S0 <= '0';
END IF;
    END PROCESS;
END A_EFC_15_S;

Another Custom Boolean Function (EFC_15_F)

The final VHDL example, EFC_15_F, demonstrates the implementation of another custom boolean function using concurrent signal assignments. It takes four standard logic inputs (M3, M2, M1, M0) and computes a single output (F2) based on a combination of AND and OR logic operations.

LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;

ENTITY EFC_15_F IS
    PORT ( M3 : IN STD_LOGIC;
           M2 : IN STD_LOGIC;
           M1 : IN STD_LOGIC;
           M0 : IN STD_LOGIC;
           F2 : OUT STD_LOGIC);
END EFC_15_F;

ARCHITECTURE A_EFC_15_F OF EFC_15_F IS
    SIGNAL N1, N2, N3, N4: STD_LOGIC;
BEGIN
    N1 <= NOT M3 AND M1 AND M0;
    N2 <= M3 AND NOT M2 AND NOT M0;
    N3 <= M3 AND NOT M2 AND NOT M1;
    N4 <= NOT M3 AND M2;
    F2 <= N1 OR N2 OR N3 OR N4;
END A_EFC_15_F;