Understanding Flip Flop and Multiplexer Designs in VHDL
Classified in Computers
Written on in 
English with a size of 3.24 KB
Flip Flop XR
library ieee;
use ieee.std_logic_1164.all;
Entity FFXR is
Port( clk, x, r : in std_logic;
q: buffer std_logic);
End FFXR;
Architecture Behavior of FFXR is
Begin
Process
Begin
Wait until clk 'EVENT' and clk='1';
if x='0' then
if r='0' then
q <= not q;
Else
If r='0' then
q <= '0';
Else
q <= q;
End If;
End If;
End Process;
End Behavior;
Multiplexer 4-to-1
library ieee;
use ieee.std_logic_1164.all;
Entity Mux_4_1 is
Port(aB: in std_logic_vector(1 downto 0);
G1N: in std_logic;
C10, C11, C12, C13: in std_logic;
G2n: in std_logic;
C20, C21, C22, C23: in std_logic;
Y1, Y2: out std_logic);
End MUX_4_1;
Architecture Behavior of MUX_4_1 is
Signal AB111: std_logic_vector(2 downto 0);
Signal AB112: std_logic_vector(2 downto 0);
Begin
ABH1 <= aB & G1n;
ABH2 <= aB & G2n;
With ABH1 select
Y1 <= C10 when "001";
C11 when "011";
C12 when "101";
C13 when "111";
'0' when others;
With ABH2 select
Y2 <= C20 when "001";
C21 when "011";
C22 when "101";
C23 when "111";
'0' when others;
end behavior;
library ieee;
use ieee.std_logic_1164.all;
PACKAGE COMPONENTS IS
Component MUX_2_1
Port (sel: in std_logic;
A, B: in std_logic_vector(3 downto 0);
GN: in std_logic;
Y: out std_logic_vector (3 downto 0));
END COMPONENT;
Component SHIFT_REG
Port(Clk, clrn, s1, s0: in std_logic;
D, C, B, A: in std_logic;
SRSI, SLSI: in std_logic;
QD, QC, Qb, QA: out std_logic);
END COMPONENT;
Component MUX_4_1
Port(AB: in std_logic_vector(1 downto 0);
G1n: in std_logic;
C10, C11, C12, C13: in std_logic;
G2n: in std_logic;
C20, C21, C22, C23: in std_logic;
Y1, Y2: out std_logic);
END COMPONENT;
END COMPONENTS;