Understanding A/D Double Ramp Converters: Principles & Operation

Understanding A/D Double Ramp Converters

Analytical relation between parameters, knowing the tension (V) acquired in the capacitor during loading, is the same as that lost during discharge. If constants are represented as 'k', then V = k * time. This expression confirms the direct relationship between the input voltage and the discharge time. When the value reaches 0, the discharge is completed, and the detector steps from 0 to A2, implying Vc = 1, ordering the transfer of the counter state at the exit.

Converter A/D Double Ramp

Its principle is the conversion of voltage to time. Both the input voltage and the reference voltage become time intervals; the relationship between the two ranges is equal to the ratio between two voltages. The core of the circuit is A1, which works as a negative integrator. Initially, and during the predetermined time T, we charge the capacitor C linearly over the input voltage Vi. The output voltage (Vh) of the integrator will be:

Since R, C, and T are constant, the final value of Vi, reached by the capacitor C after elapsed time T, will be directly proportional to the voltage Ve. The slope during loading (mc) will be greater the higher Ve.

After T, the combinational circuit control order by setting the counter to 0 and switching over to position 2. Now, the voltage applied to the integrator appears to be the Vr reference. The sign of this tension will always be contrary to the input voltage; if the input takes a positive value, Vf is negative, and vice versa. That is why now the capacitor C will discharge linearly to 0 from the previous value of the tension. The equation of the line is discharge. The slope of unloading (md) will always be identical because Vref, R, and C are invariant parameters. Representation of the operation with two existing slopes in the integrator output to Ve1 > Ve2. The drawback is that the conversion time is higher than the ramp. Download time increases the higher the value of Ve.

We obtain analytical relationships between both parameters, knowing that the capacitor voltage during charging acquired will be the same as that which is lost during download. As Vref and T are constants, prove that Ve = K • Td. Expression which confirms the direct relationship between the input voltage Ve and discharge time Td. When the value reaches 0, the download is completed, the detector steps from 0 to A2, implying, from Vc = 1, ordering the transfer of state of the counter at the exit.