Understanding Cache Memory and CPU Hazards

1. General Questions (35%)

1.1. (5%) What is the difference between a write-back cache and a write-through cache?

Write-back cache: A store only writes data to the cache and marks the corresponding line as dirty. The modified line is written to the lower level of the memory hierarchy only when it is evicted.

Write-through cache: Data is written to the caches and the memory every time a store is executed.

1.2. (15%) Name the 3 Cs in cache misses and provide a brief explanation for each C.

Compulsory miss: A cache miss caused by the first access, a cold start effect.

Capacity miss: A cache miss due to the capacity limitation. Even with full associativity, it cannot accommodate all the working sets of an application.

Conflict miss: A cache miss that occurs in a set-associative or direct-mapped cache when multiple cache lines compete for the same set. Such misses can be eliminated by employing a fully-associative cache.

1.3. (10%) What are the two kinds of locality we are exploiting in the cache? Give a brief explanation of each locality.

Temporal locality: If a data location is referenced, then it will tend to be referenced again soon.

Spatial locality: If a data location is referenced, data locations of nearby addresses will tend to be referenced soon.

1.4. (5%) What is a page fault?

An event that occurs when an accessed memory page is not present in the main memory, which requires trapping into the OS and retrieving the page from the secondary storage, such as a hard disk.

1.5. (2%) What are the differences between a write-allocate and no-write-allocate policy in a cache?

Write-allocate: When a write (store) miss occurs, the missed cache line is brought into the first level cache before the actual writing takes place.

No Write-allocate: When a write miss occurs, the memory update bypasses the cache and updates the next level memory hierarchy where there is a hit.

1.2. (2%) Explain what Control Hazard is and how to avoid it.

Control hazard: Instruction fetch depends on some in-flight instruction being executed. For example, the target address of a branch or jump is not immediately available after the branch/jump exits from the fetch stage.

Solutions:

1. Design a hazard unit to detect the hazard and stall the pipeline.
2. Branch prediction
3. Using a delay slot in the instruction scheduling

1.3. (2%) What is the primary advantage of adding a Translation Lookaside Buffer (TLB)?

A specially tailored hardware designed for accelerating address translation from virtual address space to physical address space.