Understanding the 80386 Processor State After Reset

80386 Processor State After Reset

After a reset, the 80386 processor is initialized to a specific state to ensure proper operation. Here's an explanation of the processor state after reset:

1. Operating Mode

The processor is initially in Real Mode after a reset. Real Mode is a backward-compatible mode with earlier x86 processors like the 8086/8088. In Real Mode, the processor operates with a 20-bit address bus, allowing it to address up to 1 MB of memory.

2. Segment Registers

The segment registers CS, DS, SS, and ES are set to 0x0000, pointing to the bottom of the physical memory. In Real Mode, these segment registers are 16 bits wide.

3. Instruction Pointer (IP)

The instruction pointer (IP) is set to 0xFFFF, indicating the initial address from which the processor fetches instructions. In Real Mode, the IP register is 16 bits wide.

4. Control Registers

Control registers like CR0 are initialized with default values suitable for Real Mode operation. For example, the PE (Protection Enable) bit in CR0 is cleared to disable memory protection.

5. Status Registers

Status registers like the FLAGS register are cleared to their default state, with all flags set to 0.

6. Stack Pointer (SP)

The stack pointer (SP) is set to the top of the system stack, which typically starts at the top of the physical memory and grows downward.

Debug Registers

1. DR0 to DR3

• The 80386 microprocessor has four debug registers labeled as DR0, DR1, DR2, and DR3.
• These registers are used to store linear addresses representing locations in memory where breakpoints can be set.
• Each register is 32 bits wide, allowing the storage of a 32-bit linear address.

2. DR6 (Debug Status Register)

• DR6 is the debug status register, also known as the debug control register 6.
• It contains status bits that indicate the cause of debug exceptions, such as breakpoints or other debug events.
• The bits in DR6 are used to determine which debug events have occurred and need attention.

3. DR7 (Debug Control Register)

• DR7 is the debug control register, also known as the debug control register 7.
• It is used to configure and control the behavior of debug exceptions and breakpoints.
• DR7 allows the programmer to enable or disable breakpoints, specify the type of breakpoints (instruction or data), and control debug event reporting.

Control Registers (CR0, CR1, CR2, CR3)

CR0: The lower 16-bits of CR0 are also called as MSW (Machine Status Word), for compatibility with 80286. It contains six status bits: PG (Paging Enable), ET (Extension Type), TS (Task Switched), EM (Emulation), MP (Monitor Coprocessor), PE (Protection Enable).

1. PG - Paging Enable

When PG=1, paging is enabled. When PG=0, paging is disabled.

2. ET - Extension Type

The ET bit indicates if 80387 is connected or a previous math coprocessor is connected.

3. TS - Task Switched

The processor sets this bit whenever a task switch operation is performed.

4. EM - Emulation

When EM=1, it causes INT 11 on a floating-point operation where the floating-point instruction may be emulated, when the processor does not have a floating-point unit.

5. MP - Monitor Coprocessor

On the i286 and i386 processors, the MP bit controls the function of the WAIT instruction, which makes the processor to wait for the completion of the task by math coprocessor. When it is '1', it indicates a coprocessor is connected and on wait instruction the host processor has to wait for the TEST# pin to be enabled.

6. PE - Protection Enable

When the processor enters into the protected mode it makes PE=1, and the protection mechanism is enabled. When PE=0, the processor operates in real (fast 8086) mode.

CR1: It is reserved by Intel for future use.

CR2: The CR2 register holds the 32-bit linear address that caused the last page fault detected.

CR3: The CR3 is also known as the page directory base register (PDBR).