Synchronous VHDL Testbench and CAM/SRAM Examples
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Synchronous VHDL Testbench and Modules
Structured and corrected HTML presentation of the original VHDL snippets. The original content is preserved; formatting, capitalization and minor comment grammar have been improved for readability.
Original VHDL Snippets (Preserved Content)
34
process(CLK,RST) begin
if(RST = '0') then
DATA <= (others => '0');
elsif(rising_edge(CLK)) then
if(WE = '1') then
SRAM(to_integer(unsigned(ADRESS))) <= unsigned(DATA);
else
s_data_read_reg <= std_logic_vector(SRAM(to_integer(unsigned(ADRESS))));
end if;
end if;
end process;
DATA <= s_data_read_reg when (WE = '0') else (others => 'Z')
33
process(CLK)
begin
if rising_edge(CLK) then
-- Reset síncrono
if RST = '0' then
s_reg <= (others => '0');
S <= (others => '0');
cuenta <= N;
else
-- Prioridad a la CARGA: pone el contador a 0
if CARGA = '1' then
cuenta <= 0;
end if;
-- Si el contador es menor que N, el sistema está "vivo"
if cuenta < N then
-- Desplazamiento
s_reg <= DIN & s_reg(N-1 downto 1);
-- Lógica de terminación
if cuenta = N - 1 then
S <= DIN & s_reg(N-1 downto 1);
cuenta <= N; -- Volver a reposo
else
cuenta <= cuenta + 1;
process(CLK,RST) begin
if(RST = '0') then
COUNT <= (others => '0');
dir <= '0';
elsif(rising_edge(CLK)) then
STATE <= NEXT_STATE;
if(STATE = S_OPEN) then
if(COUNT < 29) then
COUNT <= COUNT + 1;
else
COUNT <= (others => '0');
end if;
else
COUNT <= (others => '0');
end if;
if(D_FLAG = '1') then
DIR <= not(DIR);
end if;
end if;
end process;
process(STATE,REMOTE,OPEND,CLOSED,COUNT)begin
D_FLAG <= '0';
NEXT_STATE <= STATE;
case STATE is
when S_CLOSE =>
if(REMOTE = '1') then
NEXT_STATE <= UPDATE;
end if;
when UPDATE =>
NEXT_STATE <= MOVING;
D_FLAG <= '1';
when MOVING =>
if(OPEND = '1') then
NEXT_STATE <= S_OPEN;
elsif(CLOSED = '1') then
NEXT_STATE <= S_CLOSE;
end if;
if(REMOTE = '1') then
NEXT_STATE <=UPDATE;
end if;
when S_OPEN =>
if(COUNT = 29 or REMOTE = '1') then
NEXT_STATE <= UPDATE;
end if;
when others =>
NEXT_STATE <= S_CLOSE;
end case;
end process;
architecture TB of ejercicio64_tb is
signal CLK:std_logic:='0';
file f_ESTIMULOS:text is in "estimulos.txt";
file f_SALIDA:text is out "salida.txt";
signal s_VECTOR:std_logic_vector(5 downto 0);
signal s_TIEMPO:time;
signal s_PALABRA:string(0 to 7);
begin
CLK<=NOT(CLK) after 5ns;
process
variable v_LINEA:line;
variable v_TIEMPO:time;
variable v_VECTOR:std_logic_vector(5 downto 0);
variable v_PALABRA:string (0 to 9);
variable v_PARTE1:string (0 to 8):="Vector N(";
variable v_PARTE2:string (0 to 2):="): ";
variable v_PARTE3:string (0 to 0):=" ";
variable v_COUNT:integer:=0;
begin
while (NOT(ENDFILE(f_ESTIMULOS))) loop
readline(f_ESTIMULOS,v_LINEA);
read(v_LINEA,v_VECTOR);
read(v_LINEA,v_TIEMPO);
read(v_LINEA,v_PALABRA);
s_VECTOR<=v_VECTOR;
s_TIEMPO<=v_TIEMPO;
s_PALABRA<=v_PALABRA(3 downto 9);
write(v_LINEA,v_PARTE1);
write(v_LINEA,v_COUNT);
v_COUNT:=v_COUNT+1;
write(v_LINEA,v_PARTE2);
write(v_LINEA,v_VECTOR);
write(v_LINEA,v_PARTE3);
write(v_LINEA,now);
write(v_LINEA,v_PARTE3);
write(v_LINEA,v_PALABRA);
wait for 1ms;
writeline(f_SALIDA,v_LINEA);
wait until rising_edge (CLK);
end loop;
end process;
end TB;
architecture Behavioral of CAM_Sincrona is
type MEM is array (0 to (2**DEPTH) - 1) of std_logic_vector(7 downto 0);
signal CAM : MEM;
begin
process (CLK,WE) begin
if (rising_edge(CLK)) then
MATCH <= '0';
MATCH_ADDR <= (others => '0');
if (WE = '1') then
CAM(to_integer(unsigned(WR_ADDR))) <= DIN;
BUSY <= '0';
else
BUSY <= '1';
for k in 0 to 2**DEPTH -1 loop
if (CAM(k) = DIN) then
MATCH <= '1';
MATCH_ADDR <= std_logic_vector(to_unsigned(k,DEPTH));
BUSY <= '0';
32
signal REG : unsigned(3 downto 0);
begin
process (CLK, CLEAR, MODE, SERIAL, PARALLEL) begin
if(CLEAR = '0') then
REG <= "000";
OUTPUT <= "0000";
else
if (rising_edge(CLK)) then
case MODE is
when "11" => OUTPUT <= PARALLEL;
REG <= unsigned(PARALLEL);
when "01" => if (SERIAL = "01") then
OUTPUT <= '1' & std_logic_vector(REG (3 downto 1));
REG <= '1' & REG (3 downto 1);
else
OUTPUT <= '0' & std_logic_vector(REG (3 downto 1));
REG <= '0' & REG (3 downto 1);
end if;
when "10" => if (SERIAL = "10") then
OUTPUT <= std_logic_vector(REG (2 downto 0)) & '1';
REG <= REG (2 downto 0) & '1';
else
OUTPUT <= std_logic_vector(REG (2 downto 0)) & '0';
REG <= REG (2 downto 0) & '0';
end if;
when "00" => OUTPUT <= std_logic_vector(REG);
REG <= REG;
when others => OUTPUT <= std_logic_vector(REG);
REG <= REG;
-- Note: Original content ends here in the provided snippet.
end case;
end if;
end if;
end process;
Notes and Corrections
- Formatting: HTML is structured and original VHDL content is preserved inside a code block for clarity.
- Escaping: All VHDL < and > and & operators are escaped for valid HTML rendering.
- Comments: Minor grammar/capitalization adjustments were applied to non-code comments for readability (e.g., "Reset síncrono").
- Identifiers: Original identifiers and code content are left intact to avoid changing semantics.
How to Use
Copy the VHDL content from the code block into a VHDL-aware editor or simulator. Verify signal widths and identifier spellings if integrating into an existing project.