Sequential Logic: Understanding Digital Counters and Shift Registers

Digital Counters (Sequential Circuits)

Counters are sequential circuits whose output represents the number of clock pulses applied to the input. They consist of interconnected bistables (flip-flops).

Counters can operate in ascending mode (content increases with each pulse) or descending mode (content decreases).

Applications of Digital Counters

• Watches and Timers
• Frequency Dividers
• Frequency Meters (Frecuencímetro)

The maximum number of states a counter passes through is called the Modulus.

Asynchronous (Ripple) Counters

In asynchronous counters, the external clock signal is connected only to the first flip-flop. The clock input of subsequent flip-flops is connected to the output of the previous flip-flop.

This configuration causes all flip-flops not to change their state simultaneously, leading to a propagation delay (ripple effect). If the counter uses an increased number of flip-flops, the output signal frequency will be lower than the clock frequency (frequency division).

To achieve a greater number of bits, asynchronous counters are cascaded, using as many flip-flops as needed for 'k' bits.

Synchronous Counters

In synchronous counters, the external clock signal is connected to all bistables simultaneously. This ensures that all bistables change state at the same time, eliminating propagation delays.

Inconvenience: Synchronous counters require additional combinational logic to calculate the next state based on the current state.

Digital Registers (Shift Registers)

A register is a group of flip-flops used to store binary data. Shift registers allow data to be moved or shifted within the register.

Types of Shift Registers Based on I/O

Serial Input, Serial Output (SISO)

Register operation is simpler. This configuration delays the data by as many clock cycles as the number of bistables (flip-flops) in the register. This type of register is often used as a delay unit.

Serial Input, Parallel Output (SIPO)

This register receives serial input and provides parallel output information. The parallel output is available after a number of clock cycles equal to the number of flip-flops forming the register.

Its circuit is similar to the SISO shift register, but the output is taken simultaneously from all flip-flop outputs. For example, a 4-bit register outputs 4-bit data simultaneously after four clock cycles.

Parallel Input, Serial Output (PISO)

The output is obtained in series, after a period of clock cycles equal to the number of flip-flops forming the register. The utility of this register is apparent when converting parallel data to serial data, allowing transmission over a single wire.

Parallel Input, Parallel Output (PIPO)

The information is simultaneously introduced into the flip-flops. When an active edge of the clock signal occurs, the data are obtained in parallel.

Universal Registers

A Universal Register allows for all types of shift register operations (SISO, SIPO, PISO, PIPO). It typically uses two control lines connected to a multiplexer. These control lines determine how the flip-flops are interconnected and function, enabling different modes of operation.