Programmable Logic Devices: FPGA, CPLD, SPLD Explained

Fixed-function Circuits

Fixed-function circuits. They are manufactured to implement a specified logic function that cannot be altered.

Programmable Logic

Programmable logic uses devices which are manufactured to be programmed and implement different logic functions (they are alterable).

SPLD, CPLD, FPGA

SPLD — Simple Programmable Logic Device. CPLD — Complex Programmable Logic Device. FPGA — Field Programmable Gate Array.

Common Programmable Array Combinations

• PROM / RAM (Programmable Read Only Memory / Random Access Memory) — also known as a LUT (look-up table).
• Fixed AND array and programmable OR array — FPLA / PLA (Fully Programmable Logic Array / Programmable Logic Array). Both arrays, AND and OR, are programmable.

Programming Links and Technologies

Links: fuses, anti-fuses, EEPROM cells (similar to flash memory cells, but larger) or combinations of SRAM memory cells and transistors. The latter is volatile in opposition to the rest, which are nonvolatile.

CPLD Architecture and Features

• Input/Output Blocks (IOB): Configure the interface to external circuits.
• Function Blocks: They are configured (programmed) to obtain combinational and sequential functions. They contain a PLA or FPLA and 16 macrocells.
• AIM Matrix: Internal interconnection system.
• ISP (In-System Programming) and BSC (Boundary Scan Chain) controller: Allows programming (ISP) and testing (BSC) of the device directly on the board. This controller, embedded in the device, uses the JTAG (Joint Test Action Group or IEEE Std. 1149.1) serial communication protocol.

FPGA Architecture and Features

• IOB (Input/Output Blocks): Configure the interface to external circuits.
• CLB (Configurable Logic Blocks): They are configured (programmed) to obtain combinational and sequential functions.
• Block RAM and Multipliers: Memories and hardware multipliers used to implement DSP (Digital Signal Processing) algorithms at high speed with a high degree of parallelism.
• DCM (Digital Clock Manager): It manages and keeps correct synchronization of the clock signal, adjusting its phase, and multiplying or dividing its frequency.
• Interconnection System: It connects all FPGA blocks (not shown).