Processor and Memory Interface: CPU Datapath, Registers & ALU

Processor & Memory Interface

Processor & Memory Interface: The maximum size of the memory that can be used in any computer is determined by the addressing scheme. For example, a computer that generates 16-bit addresses is capable of addressing up to 2¹⁶ = 65,536 (≈ 64K) memory locations. Machines whose instructions generate 32-bit addresses can utilize a memory that contains up to 2³² = 4,294,967,296 (≈ 4G) locations, whereas machines with 64-bit addresses can access up to 2⁶⁴ ≈ 1.84 × 10¹⁹ locations. The number of locations represents the size of the address space of the computer.

The connection between the processor and its memory consists of address, data, and control lines. The processor uses the address lines to specify the memory location involved in a data-transfer operation and uses the data lines to transfer the actual data. At the same time, the control lines carry the command indicating a Read or a Write operation and whether a byte or a word is to be transferred. The control lines also provide the necessary timing information and are used by the memory to indicate when it has completed the requested operation.

Fundamental Concepts

The processor uses the Program Counter (PC) to keep track of the address of the next instruction to be fetched and executed. After fetching an instruction, the contents of the PC are updated to point to the next sequential instruction. When an instruction is fetched, it is placed in the Instruction Register (IR), where it is interpreted (decoded) by the processor's control circuitry.

Consider a 32-bit computer in which each instruction occupies one word in memory (as in many RISC architectures). To execute an instruction, the processor typically performs the following steps:

1. Fetch the contents of the memory location pointed to by the PC and load that instruction into the IR. In register-transfer notation: IR ← M[PC].
2. Increment the PC to point to the next instruction. Assuming byte-addressable memory with 32-bit (4-byte) words, the PC is incremented by 4: PC ← PC + 4.
3. Execute the operation specified by the instruction in the IR.

Fetching an instruction and loading it into the IR is usually referred to as the instruction fetch phase. Performing the operation specified in the instruction constitutes the instruction execution phase.

Single Bus Organization of Datapath in CPU

In a single-bus CPU, all the registers and the Arithmetic Logic Unit (ALU) are connected using a single internal bus that moves data inside the processor. This internal bus is different from the external bus, which connects the processor to memory for reading and writing data.

The Memory Data Register (MDR) can receive data from either the internal or external bus and can also place data on either bus. The Memory Address Register (MAR) receives an address from the internal bus and places it on the external bus to access memory. Registers R0 to Rn are programmer-visible general-purpose registers, while Y, Z, and TEMP are temporary registers used by the processor to hold intermediate data during calculations.

A multiplexer (MUX) selects either the Y output or a constant 4 for one ALU input; the constant 4 is used to increment the Program Counter (PC) to the next instruction. The instruction decoder generates signals to select registers and control data movement. The datapath—including the ALU, registers, and internal bus—performs the operations needed to run instructions. These operations include:

• Moving data between registers or between a register and the ALU.
• Fetching data from memory into a register.
• Performing arithmetic or logical operations.
• Storing results back into memory.

Using a single-bus CPU, the processor typically executes instructions sequentially, controlling the flow of data and calculations inside the CPU in a simple and organized way.

Input and Output Gating Control for Registers

Each register has two control signals: one to load data from the bus into the register and one to place data from the register onto the bus. The input and output of a register Ri are connected to the bus through switches controlled by signals Ri_in and Ri_out. When Ri_in = 1, data moves from the bus into the register. When Ri_out = 1, data moves from the register onto the bus.

For example, to transfer data from R1 to R4, set R1_out = 1 so the data is placed on the bus, and set R4_in = 1 so the data is loaded from the bus into R4.

The ALU performs operations on inputs A and B, where A typically comes from a MUX and B comes from the bus. The ALU result is stored temporarily in the Z register. The specific operation performed (addition, subtraction, logical operations) depends on the control signals.

The MDR register has four control signals: MDRin and MDRout control its connection to the internal bus, while MDRin_E and MDRout_E control its connection to the external bus.

Performing an ALU Operation (example)

To perform an ALU operation such as ADD R1, R2, R3 (R3 ← R1 + R2), the processor follows a control sequence. Each step occurs in a separate clock cycle because only one data transfer can occur on the bus at a time:

1. R1_out and Y_in are activated so the contents of R1 move into the Y register.
2. R2_out, SelectY, and the ALU Add control are activated, and Z_in stores the ALU result into Z (R1 + R2).
3. Z_out and R3_in are activated so the result in Z is moved into R3.

Fetching a Word from Memory (example)

For the instruction Move (R1), R2 (move the memory word pointed to by R1 into R2), the sequence is:

1. R1_out, MAR_in, and Read are activated to place the address from R1 into the MAR and begin the memory read operation.
2. MDR_in_E and WMFC (Wait for Memory Function Complete) are used to wait until the memory signals that the read is complete and the data is stored in MDR.
3. MDR_out and R2_in are activated to move the data from MDR into R2.

Each of the above steps requires careful control because only one data transfer can occur on the internal bus at any given clock cycle.