MIPS Overflow, Floating-Point Arithmetic, and Digital Logic

1. Half-Adder Truth Table and Circuit

For a two single-bit input, draw the truth table and corresponding circuit for the half-adder.

Truth Table

Where A and B are the input values, C is the output carry, and Σ is the sum.

(The question also requires a circuit diagram, which typically consists of an XOR gate for the Sum and an AND gate for the Carry.)

2. MIPS Overflow Handling Options

MIPS provides the following instruction options to handle overflow:

• add, addi, sub: These instructions cause an exception on overflow.
• addu, addui, subu: These instructions do not cause an exception on overflow.

3. MIPS Signed Addition Overflow Check

To avoid exceptions when performing signed addition, one can use addu and check for overflow manually. The following code logic explains how this works using instructions like addu, xor, slt, bne.

Explanation:

1. An overflow in signed addition can only occur if both operands have the same sign.
2. If the operands have opposite signs, their sum cannot overflow. An xor operation on the sign bits of the operands can detect this; if the result is negative (MSB is '1'), the signs were different, and no overflow is possible.
3. If the operands have the same sign, an overflow occurs if the sign of the result is different from the sign of the operands. An xor between an operand's sign bit and the result's sign bit can detect this change, signaling an overflow.

4. MIPS Unsigned Addition Overflow Check

The following code logic, using instructions like addu, nor, sltu, bne, can be used to check for overflow in unsigned addition.

Explanation:

For an n-bit unsigned addition of A + B, an overflow occurs if the result is greater than the maximum representable value, which is 2ⁿ - 1.

Since the n-bit register may not hold the correct sum if an overflow occurs, the condition is rearranged:

• Overflow if: A + B > 2ⁿ - 1
• This is equivalent to: B > (2ⁿ - 1) - A
• In two's complement arithmetic, the term (2ⁿ - 1) - A is equivalent to the bitwise NOT(A).
• Therefore, the condition simplifies to checking if B > NOT(A). The sltu (set on less than unsigned) instruction can be used for this comparison.

5. Saturation Operation Explained

A saturation operation is a method of handling overflow where, instead of wrapping around, the result is clamped to the largest or smallest value that can be represented.

Example:

In digital audio processing, if increasing the volume would cause an overflow, saturation arithmetic clips the signal at the maximum possible amplitude. The volume increment simply stops at the highest representable value.

6. Circuit for 32-bit Number Multiplication

Draw and appropriately label a circuit for the multiplication of two 32-bit numbers.

(This requires a diagram of a 32-bit multiplier, often implemented using an array of adders or a shift-and-add algorithm.)

7. IEEE 754 8-bit Floating-Point Representation

Following the IEEE 754 standard for an 8-bit floating-point representation with a 3-bit exponent, we can determine the binary bit patterns for -0.75 and special values.

Format Breakdown:

• Total bits: 8
• Sign bit (S): 1 bit
• Exponent bits (E): 3 bits
• Fraction bits (F): 4 bits
• Bias: 2^(3-1) - 1 = 3

Storing -0.75

1. Convert to binary: -0.75 = -3/4 = -0.11₂
2. Normalize: -1.1₂ × 2^-1
3. Determine components:
   • Sign (S): 1 (since the number is negative)
   • Exponent (E): The actual exponent is -1. The stored exponent is E + Bias = -1 + 3 = 2. In binary, this is 010.
   • Fraction (F): The part after the binary point in the normalized form is 1. With 4 fraction bits, this becomes 1000.
4. Final Bit Pattern (S EEE FFFF): 10101000

Special Values

• Zero (0): Exponent = 000, Fraction = 0000
• Positive Infinity (+∞): Sign = 0, Exponent = 111, Fraction = 0000
• Negative Infinity (-∞): Sign = 1, Exponent = 111, Fraction = 0000
• Not a Number (NaN): Exponent = 111, Fraction ≠ 0000

8. 4-Digit Decimal Floating-Point Addition Steps

Show the intermediate steps for the 4-digit decimal floating-point addition of 9.999 × 10¹ + 1.610 × 10^-1.

1. Align decimal points: The smaller exponent (-1) is adjusted to match the larger exponent (1). The significand is shifted right by 2 places (1 - (-1) = 2).
   1.610 × 10^-1 becomes 0.01610 × 10¹. The addition is now:
   9.999 × 10¹ + 0.016 × 10¹
2. Add the significands: 9.999 + 0.016 = 10.015. The result is 10.015 × 10¹.
3. Normalize the result: The result is not in scientific notation. We shift the decimal point left and increment the exponent.
   1.0015 × 10².
4. Round the significand: The significand 1.0015 has more than 4 digits. We round it to 4 digits (3 after the decimal).
   The final result is 1.002 × 10².