MIPS Hardware Multiplication and Branch Addressing Solutions

MIPS Arithmetic and Addressing Solutions

This document provides detailed solutions for problems related to MIPS arithmetic hardware (non-optimized and optimized multiplication) and MIPS instruction addressing (beq, bne, and j instructions).

Multiplication Hardware Constants

• UNSIGNED = 0
• SIGNED = 1

Non-Optimized Multiplication Hardware

Unsigned Multiplication: 10111 × 01011

Use the non-optimized multiplication hardware to perform unsigned multiplication 10111 × 01011. Show the bit value of the multiplicand, the multiplier, and the product after Step 4, separated by commas.

Answer: 0101110000, 00000, 0011111101

Signed Multiplication: 1100111 × 0011011

Use the non-optimized multiplication hardware to perform signed multiplication 1100111 × 0011011. Show the bit value of the multiplicand, the multiplier, and the product after Step 4, separated by commas.

Answer: 11111001110000, 0000001, 11111011101101

Optimized Multiplication Hardware

Signed Multiplication (Optimized): 111001 × 010011

Use the optimized multiplication hardware to perform signed multiplication 111001 × 010011. Show the bit value of the multiplicand and the product after Step 4, separated by commas.

Answer: 111001, 111110101101

Unsigned Multiplication (Optimized): 1001 × 0111

Use the optimized multiplication hardware to perform unsigned multiplication 1001 × 0111. Show the bit value of the multiplicand and the product after Step 4, separated by commas.

Answer: 1001, 00111111

MIPS Branch and Jump Addressing Calculation

Suppose the address of the first instruction is 519B27CC in hexadecimal. Show in decimal the immediate value (i.e., offset) in the beq and bne instructions, and in hexadecimal (of 7 digits) the pseudo address in the j instruction. Separate the numbers by commas.

label1:
  beq $t1, $t2, label3
  (27 instructions here)
label2:
  bne $t3, $t4, label1
  (100 instructions here)
label3:
  j label2

1. BEQ Offset Calculation (Target: label3)

The offset is the number of instructions (words) between the instruction following beq (PC + 4) and the target instruction (label3).

Instructions skipped: 27 + 1 (bne) + 100 = 128 instructions.

1st Answer (BEQ Offset): 128

2. BNE Offset Calculation (Target: label1)

The offset is the number of instructions (words) between the instruction following bne (PC + 4) and the target instruction (label1). Since this is a backward jump, the offset is negative.

Instructions jumped backward: 1 (beq) + 27 (instructions) + 1 (bne itself) = 29 instructions relative to PC+4 of bne.

2nd Answer (BNE Offset): -29

3. J Instruction Pseudo Address Calculation (Target: label2)

Step A: Determine Address of label2

The address of label1 (beq) is 519B27CC.

The address of label2 (bne) is 28 instructions later (1 beq + 27 instructions).

Offset in bytes: 4 × 28 = 112 (decimal).

Address of label2 = 519B27CC + 112 (decimal).

519B27CC + 112 → Convert 112 to Hexadecimal (70).

(Reference MIPS green sheet for conversion details.)

Address of label2: 519B283C

Step B: Calculate the 26-bit Target Field

The target address is 519B283C. The 26-bit field is derived by dropping the upper 4 bits and the lower 2 bits (dividing the address by 4).

Convert the lower 28 bits (19B283C) to binary:

1 0001 9 1001 B = 111011 2 0010 8 1000 3 0011 C = 12 1100

Shift to the right two spaces (to get the 26-bit field):

Original (30 bits shown): 0001 1001 1011 0010 1000 0011 1100

Shifted (26 bits, padded): 00 00 01 10 01 10 11 00 10 10 00 00 11 11

Hexadecimal representation of the 26-bit field: 066CA0F

3rd Answer (J Pseudo Address, 7 digits): 066CA0F