Microcontrollers: Architecture, Instruction Sets, and Interfacing

Microcontrollers, Microcomputers, and Microprocessors

Microcontroller: Processor, memory, and I/O ports integrated on a single chip.

Microcomputer: A small computer.

Microprocessor: Example: Intel x86.

Von Neumann Architecture

Components:

• Processor (Control Unit, ALU, Registers)
• Memory (RAM - Volatile, ROM - Non-Volatile)
• I/O

A single bus interconnects the processor, memory, and I/O.

RISC vs. CISC

RAM vs. ROM vs. CPU Register

Functional Units

• ALU: Logic circuits for arithmetic and logic operations (addition, subtraction, AND, OR, etc.).
• Control Unit: Timing and control circuits for fetching program instructions and data from memory sequentially.
• Registers: Typically 16 or 32 registers for holding data, addresses, etc.

TM4C123

• Microprocessor – Instruction Set: CISC vs. RISC
• Memory:
  • Non-Volatile: ROM, EPROM, EEPROM
  • Volatile: RAM (DRAM, SRAM)
• I/O Interfaces: Parallel, Serial, Analog, Time

Cortex-M4 Architecture and Related Concepts

1. Cortex-M4 architecture
2. Von Neumann vs. Harvard architecture
3. Cortex-M instruction set features
4. TM4C memory address space
5. Big and little endian

Assembly Language Programming

1. Cortex-M assembly instructions
2. Assembly addressing modes
3. Understanding assembly programs

Input/Output (IO) with TM4C

1. TM4C I/Os
2. I/O register address calculation
3. I/O port initialization and coding (direct register access)
4. Friendly software (set, clear, toggle)
5. LED and switch interfacing
6. Positive and negative logic

Advanced I/O and Interrupts

1. Bit-specific addressing
2. Generating delays using SysCtlDelay()
3. GPIOPinRead()/GPIOPinWrite()

Clocks and Interrupts

1. Generating specific clock frequencies using SysCtlClockSet()
2. Interrupt concepts
3. Interrupt conditions
4. Interrupt vector table
5. Edge-triggered interrupt configuration

Interrupt Handling

1. Interrupt context switch
2. Shared interrupt vector

Timers and Periodic Interrupts

1. Periodic interrupt configuration
2. General purpose timer configuration for periodic interrupts