LEGv8 Architecture and Assembly Language: Key Concepts

Performance Metrics

• Elapsed Time: Represents overall system performance. It is the total time taken to complete a task.
• User CPU Time: Indicates CPU performance. It is the time the task actively runs on the CPU, excluding idle time.
• CPU Time: The time the CPU spends executing instructions, either from the task or the operating system, excluding idle time.
• Clock Speed: 1 MHz equals 1 million clock cycles per second. 1 GHz equals 1 billion clock cycles per second.
• Response Time: Equivalent to execution time.
• Throughput: Equivalent to bandwidth.
• Performance Comparison: (PerfA) / (PerfB) = (ExecTimeB) / (ExecTimeA) = n

Impact of Processor Upgrades

• Replacing a processor with a faster one decreases response time and increases throughput.
• Adding an additional processor, assuming no queuing, increases throughput.
• Adding an additional processor, with queuing, decreases response time and increases throughput.

Registers and Memory

• LEGv8 architecture utilizes 32 registers (X0, X1, ..., X30, XZR).
• It also supports 2⁶² memory words.
• Each register in LEGv8 is 64 bits in size.
• A group of 64 bits (8 bytes) is termed a "doubleword" in LEGv8. A group of 32 bits is called a "word".

Design Principles

• Design Principle 1: Simplicity favors regularity.
• Design Principle 2: Smaller is faster.

Increasing the number of registers might enhance an assembly program but could potentially reduce the clock frequency.

Registers reside within the processor, while data structures are stored in memory.

If array A has a base address of 2000, A[0] is at address 2000. Therefore, A[1] would be at address 2008.

The number of registers grows only as new instruction sets become viable.

Bit Significance

• Least Significant Bit: The rightmost bit in a LEGv8 doubleword.
• Most Significant Bit: The leftmost bit in a LEGv8 doubleword.

A LEGv8 doubleword, being 64 bits long, can represent 2⁶⁴ distinct 64-bit patterns.

Signed Number Representation

To obtain the decimal equivalent of a signed negative number, use the following method:

Example: 11111111 11111111 11111111 11111111 11111111 11111111 11111111 11111100

(1 x -2⁶³) + (1 x 2⁶²) + ... + (0 x 2⁰) = -4

A signed load extends the sign to fill the remaining bits of the register, ensuring a correct representation of the number. This is called sign extension.

Unsigned load: LDURB, Signed load: LDURSB

Overflow

Overflow (OV) occurs only when adding two positive numbers results in a negative number (0(+) + 0(+) = 1(-)) or when adding two negative numbers results in a positive number (1(-) + 1(-) = 0(+)).

Instruction Formats

R-Format (ADD, SUB, LSL, LSR)

OpCode(11 bits) | Rm(5 bits) | Shamt(6 bits) | Rn(5 bits) | Rd(5 bits)

Note: Rm is unused during shift operations.

I-Format (ADDI, SUBI)

OpCode(10 bits) | Immediate(12 bits) | Rn(5 bits) | Rd(5 bits)

D-Format (LDUR, STUR)

OpCode(11 bits) | Address(9 bits) | Op2(2 bits) | Rn(5 bits) | Rt(5 bits)

Shift Operations

• A dual shift left is equivalent to a shift right.
• Shift left is used for multiplication. Shifting left by 4 bits is the same as multiplying by 16.

Logical Operations

• AND with 0s and OR with 1s.
• AND can isolate a field within a doubleword.
• A shift left followed by a shift right can also isolate a field in a doubleword.

Branching

CBZ: Compare and Branch if Zero.

Example: if-else Statement

if (i == j) f = g + h; else f = g - h

SUB X9, X22, X23
CBNZ X9, Else
ADD X19, X20, X21
B exit
Else: SUB X19, X20, X21
exit:

Example: while Loop

while (save[i] == k) i += 1;

Loop: LSL X10, X22, #3 // Temp reg X10 = i * 8
ADD X10, X10, X25 // X10 = address of save[i]
LDUR X9, [X10, #0] // Temp reg X9 = save[i]
SUB X11, X9, X24 // X11 = save[i] - k
CBNZ X11, Exit // Exit if save[i] != k (X11 != 0)
ADDI X22, X22, #1 // i = i + 1
B Loop // Go to loop
Exit: