Fundamental Computer Architecture Concepts

Common Bus System Explained

The common bus system is an architecture where a single bus is used for communication between various components of a computer, such as memory, registers, and the ALU. This system minimizes the number of pathways required, thereby simplifying the design and saving space.

Components of a Common Bus System:

• Set of Registers (R1, R2, ...)
• Arithmetic Logic Unit (ALU)
• Control Unit
• Common Bus
• Memory Unit

Operation of a Common Bus System:

• Only one register can place its contents on the bus at a time.
• A control unit uses selection lines and control signals to manage data transfers.
• A multiplexer selects which register’s data will go onto the bus.
• A decoder selects the destination register to receive the data.

Advantages:

• Reduces hardware cost
• Simplifies control logic

Tri-State Buffer Functionality

A tri-state buffer allows a circuit to output three types of signals: logic 0, logic 1, and a high-impedance (Z) state. The high-impedance state effectively removes the device’s output from the circuit, allowing multiple outputs to share the same line without interference.

Working Principle:

• Input = A
• Enable = E
• Output = A if E=1, Z if E=0

Key Use:

Crucial in bus systems to prevent data conflicts.

Hardware Implementation of Logic Operations

Logic micro-operations perform bitwise logical operations (e.g., AND, OR, XOR, NOT) on the contents of registers.

Implementation Details:

• Utilize logic gates between each bit of source and destination registers.
• Each pair of bits passes through a dedicated gate to produce the output.

Example:

Consider an AND operation between two registers:

• R1 = 1010
• R2 = 1100
• Result (R1 AND R2) = 1000

Stored Program Organization Principles

Stored Program Organization is a fundamental computer architecture concept where both program instructions and data are stored in the same memory space. The control unit fetches instructions from memory one by one, decodes them, and then executes them. This model is primarily based on the renowned Von Neumann architecture.

Illustrative Example:

Consider a simple program designed to add two numbers:

Memory will store:

• Instruction 1: Load A (Load value of A into accumulator)
• Instruction 2: Add B (Add value of B to accumulator)
• Instruction 3: Store C (Store accumulator content into C)
• Data: A = 5, B = 3

Memory Reference Instructions Explained

Memory Reference Instructions (MRIs) are a class of CPU instructions that directly involve operations with the computer's main memory. These instructions facilitate data transfer and manipulation between the CPU and memory locations.

Common Memory Reference Instructions:

1. AND: Performs a logical AND operation between memory content and the accumulator.
2. ADD: Adds the content of a memory location to the accumulator.
3. LDA (Load Accumulator): Loads the content of a memory location into the accumulator.
4. STA (Store Accumulator): Stores the content of the accumulator into a specified memory location.
5. BUN (Branch Unconditionally): Transfers program control unconditionally to a specified memory address.
6. BSA (Branch and Save Return Address): Branches to a subroutine, saving the return address for later use.
7. ISZ (Increment and Skip if Zero): Increments the content of a memory location and skips the next instruction if the result is zero.

Understanding CPU Interrupts and Types

An Interrupt is a signal that temporarily halts the CPU's current task, allowing it to address a higher-priority task or respond to an urgent event. This mechanism is crucial for efficient multitasking and responsiveness in computer systems.

Different Types of Interrupts:

1. Hardware Interrupt: Generated by hardware devices (e.g., keyboard, mouse, disk drive) to signal completion of an I/O operation or an error.
2. Software Interrupt: Initiated by a program to request operating system services (e.g., system calls) or to handle specific conditions.
3. Internal Interrupt (Trap): Caused by illegal or exceptional operations within the CPU, such as a divide-by-zero error, invalid memory access, or overflow.
4. External Interrupt: Originates from external hardware signals, often from peripheral devices, timers, or power failure detection circuits.
5. Maskable Interrupt: An interrupt that the CPU can ignore or delay if it is currently processing a more critical task. Its processing can be enabled or disabled.
6. Non-Maskable Interrupt (NMI): A high-priority interrupt that cannot be ignored or delayed by the CPU. NMIs are reserved for critical system events like memory parity errors or power supply failures.