Electronic Circuit Fundamentals: Timers, PLLs, and Filter Characteristics

Capacitor-Based Timing Circuit Operation

• Initially, the capacitor is uncharged.
• When Vcc is applied, an internal transistor is held off, and the output goes high.
• The external capacitor 'C' charges through resistors RA and RB with a time constant of (RA + RB)C. When the voltage across the capacitor reaches 1/3 Vcc, the trigger comparator provides a low output, which sets an internal flip-flop. This action typically causes the main output to go high and keeps the discharge transistor off.
• Subsequently, the capacitor voltage continues increasing towards Vcc. When it reaches 2/3 Vcc, the upper comparator's output becomes high. This logical state resets the flip-flop, causing the output to turn off (go low). Simultaneously, an internal transistor turns on, allowing the capacitor to discharge.

Digital Frequency Dividers in PLLs

• A digital frequency divider is inserted between the VCO and the phase comparator in a PLL feedback loop.
• Since the output of the divider is locked to the input frequency (fin), the VCO is actually running at a multiple of the input frequency.
• The desired amount of frequency multiplication can be achieved by selecting a proper divide-by-N network, where N is an integer.
• For example, to obtain an output frequency (fout) that is five times the input frequency (fout = 5 * fin), a decade counter like the IC 7490 can be used as the divide-by-N network. The IC 7490 can also be utilized as a driver stage to increase driving capacity, for instance, when interfacing with an NE565.