Digital Logic Design: Examples in VHDL
Classified in Computers
Written at on 
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Behavioral Architecture of a State Machine
This VHDL code describes the behavioral architecture of a state machine.
TYPE tipo_estado IS (DET0, DET0a1, DET1a0, DET1);
signal Estado_actual : tipo_estado;
signal Estado_siguiente : tipo_estado;
begin
Registro_estado: process (clk, reset)
begin
if reset='1' then
Estado_actual <= DET0;
elsif (clk'event and clk='1') then
Estado_actual <= Estado_siguiente;
end if;
end process Registro_estado;
Cambio_Estado: process (Dato, Estado_actual)
begin
Estado_siguiente <= Estado_actual;
case Estado_actual is
when DET0 =>
if (Dato='1') then
Estado_siguiente <= DET0a1;
else
Estado_siguiente <= DET0;
end if;
when DET0a1 =>
if (Dato='1') then
Estado_siguiente <= DET1;
else
Estado_siguiente <= DET1a0;
end if;
when DET1a0 =>
if (Dato='1') then
Estado_siguiente <= DET1a0;
else
Estado_siguiente <= DET0;
end if;
when DET1 =>
if (Dato='1') then
Estado_siguiente <= DET1;
else
Estado_siguiente <= DET1a0;
end if;
when others => Estado_siguiente <= DET0;
end case;
end process Cambio_estado;
Salidas: process (Estado_actual)
begin
case Estado_actual is
when DET0 => FA_Dato <= '0'; FD_Dato <= '0'; F_Dato <= '0';
when DET0a1 => FA_Dato <= '1'; FD_Dato <= '0'; F_Dato <= '1'
;
when DET1a0 => FA_Dato <= '0'; FD_Dato <= '1'; F_Dato <= '1';
when DET1 => FA_Dato <= '0'; FD_Dato <= '0'; F_Dato <= '0';
when others => FA_Dato <= '0'; FD_Dato <= '0'; F_Dato <= '0';
end case;
end process Salidas;
end Behavioral;
Behavioral Architecture of a 2-bit Counter
architecture Behavioral of ctr_2_bits is
signal q_dentro :std_logic_vector(1 downto 0);
begin
process(din,ce,clk,load,reset,q_dentro)
begin
if (rising_edge(clk)) then
if(reset = '1') then q_dentro <= "00";
elsif (load = '1') then q_dentro <= din;
elsif(ce = '0') then q_dentro <= q_dentro;
else q_dentro <= q_dentro + 1;
end if;
end if;
if (q_dentro = "11") then tc <= '1';
else tc <= '0';
end if;
if (q_dentro = "11" and ce = '1') then ceo <= '1';
ELSE ceo <='0';
end if;
end process;
q <= q_dentro;
end Behavioral;
Sequential Logic Equations
Q t+1 = EN ∙ D + EN' ∙ Qt
Q t+1 = S + R' Qt
Q t+1 = J ∙ Qt' + K '∙ Qt
Qt+1 = Qt'
Behavioral Architecture of a Right Shift Register
architecture Behavioral of reg_desplazamiento_derecha is
signal temp: std_logic_vector(7 downto 0);
begin
process (clk,reset,load,msb_in,shift_enable,data_in)
begin
if reset='1' then
temp<="00000000";
lsb_out<=temp(0);
elsif (clk'event and clk='1') then
if(load='1') then
temp<=data_in;
lsb_out<=temp(0);
elsif(load='0' and shift_enable='0') then
temp<=temp;
lsb_out<=temp(0);
elsif(load='0' and shift_enable='1') then
lsb_out<=temp(0);
temp<=(msb_in & temp(7) & temp(6) & temp(5) & temp(4) & temp(3) & temp(2) & temp(1));
end if;
end if;
end process;
q_shift<=temp;
end Behavioral;
Behavioral Architecture of a JK Flip-Flop
architecture Behavioral of ej1 is
signal temp: std_logic;
begin
process (clk,ce,J,K,reset)
begin
if rising_edge(clk) then
if reset='1' then
temp <= '0';
elsif ce ='1' then
if (J='0' and K='0') then
temp <= temp;
elsif (J='0' and K='1') then
temp <= '0';
elsif (J='1' and K='0') then
temp <= '1';
elsif (J='1' and K='1') then
temp <= not (temp);
end if;
end if;
end if;
end process;
q <= temp;
end Behavioral;
Behavioral Architecture of a Simple ALU
architecture Behavioral of ejercicio2 is
COMPONENT funcion_and_4_bits
PORT(
a : IN std_logic_vector(3 downto 0);
b : IN std_logic_vector(3 downto 0);
resultado1 : OUT std_logic_vector(3 downto 0)
END COMPONENT;
COMPONENT mux_4_canales_8_bits
PORT(
canal_0_mux : IN std_logic_vector(7 downto 0);
canal_1_mux : IN std_logic_vector(7 downto 0);
canal_2_mux : IN std_logic_vector(7 downto 0);
canal_3_mux : IN std_logic_vector(7 downto 0);
sel : IN std_logic_vector(1 downto 0);
mux_out : OUT std_logic_vector(7 downto 0)
END COMPONENT;
signal res_and : std_logic_vector(7 downto 0);
begin
Inst_mux_4_canales_8_bits: mux_4_canales_8_bits PORT MAP(
canal_0_mux => res_and ,
canal_1_mux => res_complemento ,
canal_2_mux => res_resta ,
canal_3_mux => res_producto ,
sel => sel,
mux_out => resultado
Inst_funcion_and_4_bits: funcion_and_4_bits PORT MAP(
a => a,
b => b,
resultado1 => res_and1
res_and <= (res_and1(3) & res_and(3) & res_and1(3) & res_and1(3) & res_and1);
end Behavioral;