Digital Hardware Design Reference: SystemVerilog and Architecture Fundamentals

SystemVerilog Fundamentals

• logic Data Type: Supports 4 states (0, 1, X, Z).
• Legacy Types: Replace old Verilog reg/wire with logic in SystemVerilog (SV).

• Always Blocks

  • Combinational Logic: always_comb begin ... end
  • Sequential Logic: always_ff @(posedge clk or posedge rst) begin ... end

• Assignments

  • Blocking Assignment (=): Sequential execution. Use in combinational logic (always_comb).
  • Non-blocking Assignment (<=): Parallel execution. Essential for sequential logic (always_ff).

• Module Definition Example

  module m(input logic a, b, output logic y);
  assign y = a & b;
  endmodule

• Concatenation: {a, b, c}
• Replication: {8{in[7]}} (Repeats the specified bit 8 times, often used for sign extension).

Testbench Development

• Instantiate the Device Under Test (DUT) inside the testbench module.
• Use initial begin ... end blocks for generating stimuli.

• Self-Checking Mechanisms

  Compare output against expected values:

  if (out !== expected) $error("Fail: got %b", out);

• Debugging Utilities: Use $display and $monitor for waveform analysis and logging.

Numbers and Data Formats

• Binary and Hexadecimal Constants: Examples include 4'b1010 and 8'hFF.
• Sign Extension: Used to widen a signed number while preserving its value: { {n{val[msb]}}, val }

• Two’s Complement Representation

  • Negation: Invert all bits and add 1.
  • Range (n bits): $-2^{(n-1)}$ to $2^{(n-1)}-1$.

• Q Format (Fixed-Point Arithmetic)

  • Format Qm.n: $m$ integer bits and $n$ fractional bits.
  • Multiplication Rule: $Q_{m.n} \times Q_{m.n} = Q_{(2m).(2n)}$. Requires shifting the result right by $n$ bits.

• Floating Point (IEEE 754 Single Precision)

  • 32-bit Structure: 1 sign bit, 8 exponent bits (with bias 127), 23 mantissa bits.
  • Value Calculation: $(-1)^s \times (1.M) \times 2^{(E-127)}$

Arithmetic Logic Unit (ALU) Design

• Adders

  • Ripple-Carry Adder: Simple structure, but slow due to carry propagation delay.
  • Carry-Lookahead Adder: Faster performance, requires more hardware complexity.
  • Prefix Adders (Kogge-Stone, etc.): Advanced high-speed structures.
  • Tradeoff: Increased speed generally leads to increased hardware cost.

• ALU Operations and Flags

  • Common Operations: Addition, Subtraction, AND, OR, Set Less Than (slt), Shifts.

  • Condition Flags

    • Zero (Z): Set if the result is zero.
    • Negative (N): Set if the Most Significant Bit (MSB) of the result is 1.
    • Overflow (V): Indicates signed arithmetic overflow (sign mismatch during addition).
    • Carry (C): Indicates unsigned carry out from the MSB.

  • Overflow Detection (Two’s Complement)

    • Addition: Overflow occurs if inputs have the same sign, but the result has a different sign.
    • Subtraction: Overflow occurs if input signs differ, and the result sign matches the subtrahend's original sign.

Instruction Set Architecture (ISA) - RISC-V Style

• Instruction Formats

  • R-type: Register-to-Register operations (op rd rs1 rs2 funct)
  • I-type: Immediate operations (op rd rs1 imm)
  • S-type: Store operations
  • B-type: Branch operations (PC-relative addressing)
  • J-type: Jump operations
• Registers: 32 general-purpose registers. Key registers: x0 (always zero), x1 (return address, ra), x2 (stack pointer, sp).
• Control Flow Instructions: beq, bne, blt, j, jal, jr.

• Instruction Examples

  add x5, x1, x2  # R-type: x5 = x1 + x2
  lw x3, 8(x4)    # I-type: Load word into x3 from memory address x4 + 8
  sw x3, 0(x5)    # S-type: Store word from x3 to memory address x5 + 0
  beq x1, x2, L   # B-type: Branch to label L if x1 == x2
  jal x1, target  # J-type: Jump to target, save return address in x1

• Recursion and Stack Management: Function calls require pushing arguments and the return address (ra) onto the stack before the call, and popping them upon return.

Memory Hierarchy and Caching

• SRAM vs. DRAM

  • SRAM (Static RAM): Fast, expensive, used primarily for cache memory.
  • DRAM (Dynamic RAM): Dense, slower, used for main system memory.

• Cache Concepts

  • Block: Also known as a cache line. The minimum unit of data transfer.
  • Miss Penalty: The time required to fetch a block from a lower level of the memory hierarchy.
  • Locality: Principles that improve cache performance: temporal locality (reusing data soon) and spatial locality (accessing nearby data).

Finite State Machines (FSM)

• Moore Machine: Outputs depend solely on the current state.
• Mealy Machine: Outputs depend on the current state and the current inputs.

• HDL FSM Skeleton

  typedef enum logic [1:0] {S0, S1, S2} state_t;
  state_t state, next;
  
  // Sequential block (State Register)
  always_ff @(posedge clk) begin
      state <= next;
  end
  
  // Combinational block (Next State Logic)
  always_comb begin
      case(state)
          S0: if(x) next = S1; else next = S0;
          // ... other states
      endcase
  end

Example Conversions

• Two’s Complement (8-bit Examples)

  • 01101011 = 107 (Positive)
  • 11101011 = -21 (Negative)

• Q3.4 Fixed-Point Format

  • 0101.1100 = 5.75 (3 integer bits, 4 fractional bits)

• IEEE 754 FP32 Example

  0 10000001 01000000000000000000000

  • Sign (s) = 0 (Positive)
  • Exponent (E) = 129. Normalized Exponent = $E - 127 = 2$.
  • Mantissa (M) = 1.25
  • Value = $1.25 \times 2^2 = 5.0$

Common Design Pitfalls

• Assignment Errors: Do not mix blocking (=) and non-blocking (<=) assignments incorrectly.
• Sign Extension: Carefully manage sign extension, especially when dealing with immediate values in ISA.
• Flags Distinction: Remember that Overflow (signed) is not the same as Carry (unsigned).
• PC Addressing: The Program Counter (PC) is byte-addressed, but branch offsets are typically word-aligned (multiples of 4 bytes).
• Function Calls: For recursion, ensure both the return address (ra) and local variables are saved onto the stack.

SystemVerilog Constant Formatting

Format: <size>'<base><value>

Bases: b (binary), h (hexadecimal), d (decimal)

Steps for Interpretation:

1. Note the size, which defines the total number of bits.
2. Convert the value into its decimal equivalent.

Example: 8'b1000_1010

• Bits = 8.
• Decimal Value = $128 + 8 + 2 = 138$.

Two’s Complement to Decimal Conversion

Steps:

1. Check the Most Significant Bit (MSB): 0 indicates positive, 1 indicates negative.
2. If MSB = 0, convert the number normally.
3. If MSB = 1 (Negative):
   1. Invert all bits.
   2. Add 1 to the result.
   3. Convert this final value to decimal and apply a negative sign.

Example: 4'b1011

• MSB = 1 (Negative).
• Invert: 0100.
• Add 1: 0101.
• Decimal = 5.
• Final Value = -5.

Decimal to Q Format (Fixed-Point) Conversion

Format $Q_{m.n}$ requires $m$ integer bits and $n$ fractional bits.

Steps:

1. Multiply the decimal value by $2^n$.
2. Convert the resulting integer to binary.
3. If the original decimal was negative, apply two’s complement to the binary result.
4. Convert to hexadecimal if required.

Example: Convert -13.5625 to $Q_{8.8}$

• $-13.5625 \times 2^8 = -3472$.
• In 16-bit two’s complement, $-3472$ is 0xF240.

Q Format to Decimal Conversion

Steps:

1. Interpret the entire bit string as a signed integer.
2. Divide the resulting integer value by $2^n$ (where $n$ is the number of fractional bits).

Example: 0101.1000 ($Q_{4.4}$)

• Binary interpreted as signed integer = 88.
• Decimal = $88 / 2^4 = 88 / 16 = 5.5$.

Decimal to IEEE 754 Float (Single Precision) Conversion

Format: 1 sign bit, 8 exponent bits (bias 127), 23 mantissa bits.

Steps:

1. Determine the Sign Bit (0 for positive, 1 for negative).
2. Convert the absolute value of the number to binary.
3. Normalize the binary number into the form $1.x \times 2^E$.
4. Calculate the Exponent Field: $E_{field} = E + 127$.
5. The Mantissa (M) is the fraction bits ($x$) following the leading 1. Pad with zeros to 23 bits.
6. Combine the fields and convert the final bit string to hexadecimal.

Example: Convert 42.3125

• Binary: $101010.0101$.
• Normalized: $1.010100101 \times 2^5$. (Thus, $E=5$).
• Sign = 0.
• Exponent Field = $5 + 127 = 132$ (Binary: 10000100).
• Mantissa = 010100101... (padded).
• Hexadecimal Result = 0x422A4000.