1. JK Flip-Flop Operation and Truth Table

Logic Diagram:

Working Principle

The JK flip-flop is an enhanced version of the gated SR flip-flop. It incorporates clock input circuitry to eliminate the invalid output condition that occurs when both S and R inputs are logic level "1".

Because of the added clock input, the JK flip-flop offers four distinct input combinations:

• Logic "1" (Set)
• Logic "0" (Reset)
• No Change
• Toggle

The S and R inputs of the preceding SR bistable are replaced by J and K inputs, named after its inventor, Jack Kilby. Thus, J = S and K = R.

The two 2-input AND gates in the gated SR bistable are replaced by two 3-input NAND gates. The third input of each NAND gate connects to the outputs Q and $\bar{Q}$. This cross-coupling allows the previously invalid state (S=1, R=1) to produce a toggle action as the inputs become interlocked.

• If the circuit is set (J=1, K=0), the J input is inhibited by the $\bar{Q}=0$ status through the lower NAND gate.
• If the circuit is reset (J=0, K=1), the K input is inhibited by the $Q=0$ status through the upper NAND gate.

Since Q and $\bar{Q}$ are always complementary, they control the inputs effectively. When both inputs J and K are equal to logic "1", the JK flip-flop toggles.

2. 4-Bit SISO Shift Register Operation

Diagram (using D-type flip-flops):

Working Principle

The Serial-In Serial-Out (SISO) shift register transmits data one bit at a time serially. It features three primary connections:

1. Serial Input (SI): Determines the bit entering the leftmost flip-flop.
2. Serial Output (SO): Taken from the output of the rightmost flip-flop.
3. Sequencing Clock Signal (Clk).

In the generalized diagram below, the outputs are designated as: FFA output is $Q_D$, FFB $Q_C$, FFC $Q_B$, and FFD $Q_A$ (assuming data flows left to right).

Waveform (Input: 01101)

c) 4-Bit R-2R Ladder DAC Circuit and Output Expression

Ans:

5. Successive Approximation ADC Working and Parameters

Circuit Diagram:

Working Principle

When the start signal goes low, the Successive Approximation Register (SAR) is cleared, setting the DAC output voltage ($V_{DAC}$) to 0V. When start goes high, conversion begins.

1. First Clock Pulse: The control circuit sets the Most Significant Bit (MSB) of the SAR to '1'. The SAR output becomes 10000000. This is fed to the DAC, producing an analog output ($V_{DAC}$).

2. Comparison: $V_{DAC}$ is compared with the unknown analog input voltage ($V_{in}$).

• If $V_{DAC} > V_{in}$, the comparator output is $-V_{sat}$, and the MSB is reset to '0'.
• If $V_{DAC} < V_{in}$, the comparator output is $+V_{sat}$, and the MSB is kept at '1'.

3. Subsequent Pulses: Assuming the MSB is kept set (1), the next clock pulse sets the next bit ($D_6$) to '1', resulting in a SAR output of 11000000. $V_{DAC}$ is recalculated and compared with $V_{in}$. This process of checking and deciding whether to keep a bit set or reset continues down to the Least Significant Bit ($D_0$).

4. Completion: After $N$ clock cycles (where $N$ is the number of bits), the DAC input holds the digital data equivalent to the analog input. The control circuit then signals the end of conversion, and the data is locked in the buffer register.

Resolution

Resolution is defined as the smallest change in the analog input voltage necessary to cause a one-bit change in the digital output.

Conversion Time

Conversion time is the total time required for the ADC to convert an analog input voltage into a stable digital output.

6. Subtraction using 2's Complement Method

Calculate: $(35)_{10} - (5)_{10}$

Ans:

7. Radix of Number Systems

Ans: Radix of:

• Binary: 2
• Octal: 8
• Decimal: 10
• Hexadecimal: 16

8. Necessity of a Multiplexer

Ans:

• It reduces the number of wires required to transmit data from multiple sources to a single destination.
• It minimizes the complexity of the hardware circuit.
• It simplifies overall logic design.
• In digital systems requiring transmission of many signals simultaneously over a single line, a multiplexer is essential.
• It reduces cost by avoiding the need for separate dedicated lines for every signal.

9. Modulus of a Counter

Ans: The modulus of a counter is defined as the total number of unique states or clock cycles the counter cycles through before returning to its initial state.

• The number of flip-flops required for a Mod-6 counter is 3 ($2^2 < 6 \le 2^3$).

10. Function of Preset and Clear in Flip-Flops

Ans:

• When power is initially switched on, the state of a flip-flop circuit is uncertain (Q could be 1 or 0).
• The function of the Preset input is to force the flip-flop into a known state where $Q = 1$ (Set).
• The function of the Clear input is to force the flip-flop into a known state where $Q = 0$ (Reset).

11. De Morgan's Theorems

Ans:

De Morgan's 1st Theorem

The complement of a sum is equal to the product of their individual complements.

$\overline{A+B} = \bar{A} \cdot \bar{B}$

De Morgan's 2nd Theorem

The complement of a product is equal to the sum of their individual complements.

$\overline{A \cdot B} = \bar{A} + \bar{B}$

12. Convert Expression to Standard SOP Form

Expression: $Y = AB + \bar{A} + BC$

13. Working of 4-Bit Universal Shift Register

Working Modes

A universal shift register can perform parallel load, shift right, and shift left operations, controlled by mode inputs (M).

1. Parallel Load: When the mode control (M) is set to logic '1', AND gates 2, 4, 6, and 8 are enabled, while AND gates 1, 3, 5, and 7 are disabled. The 4-bit binary data is loaded in parallel. The clock input transfers this parallel data to the outputs ($Q_A$ to $Q_D$).
2. Shift Right: When mode control (M) is set to logic '0', AND gates 1, 3, 5, and 7 are enabled, while gates 2, 4, 6, and 8 are disabled. Data shifts serially. The clock input applies to the flip-flops, enabling the right shift path (gate 9) and disabling the left shift path (gate 10). Data moves serially from $Q_A$ towards $Q_D$.
3. Shift Left: This operation is typically achieved by connecting the output of each flip-flop to the parallel input of the preceding flip-flop, and applying serial input at the appropriate end, often utilizing the same mode control setting as parallel load, but routing the clock differently or using a separate control signal depending on the specific design.

14. Realize Logic Expressions Using Only NAND Gates

Ans: