CPU Terminals, Buses, and Instruction Execution Cycle

CPU Terminals and Bus Interconnection

The terminals (pins) of a Central Processing Unit (CPU) are typically divided into three main types: Address, Data, and Control.

These terminals are connected to similar terminals on memory chips and Input/Output (I/O) devices. This interconnection is collectively known as the bus system.

Communication between the CPU, memory, and I/O devices is effective through both transmitting and receiving signals at these terminals.

Key Bus Parameters

The functionality of the bus system is defined by three basic parameters:

• Address Lines: A chip that has m address lines can address up to 2^m memory locations.
• Data Lines: A chip that has n data lines can write or read a word of n bits in a single operation.
• Control Lines: These regulate the flow and timing of data entering and leaving the CPU, among other uses.

Other essential CPU connections include:

• Power terminals
• Clock signal (typically a square wave)

Control and Arbitration Signals

• Control Bus Signals: These are primarily outputs from the CPU (inputs to memory chips and I/O devices) that indicate whether the CPU intends to read from or write to memory, or perform another specific operation.
• Interrupts: Signals used by I/O devices to request attention from the CPU.
• Bus Arbitration: Mechanisms that regulate traffic on the bus, preventing two devices from attempting to use the bus simultaneously.
• Coprocessor Support: Some CPU architectures are designed to operate efficiently with specialized coprocessors, such as floating-point units (FPUs) or dedicated graphics processors.

Defining the System Bus

A bus is an electrical pathway designed for communication between multiple devices.

• Buses can carry data internally within the CPU or facilitate external communication between the CPU, memory, and I/O devices.
• Buses are classified according to their functionality (e.g., Address Bus, Data Bus, Control Bus), facilitating communication with memory and I/O.

Bus Width and Addressing Capacity

The width of a bus is a critical parameter. The more address lines a bus has, the more memory the CPU can directly address.

• If an address bus has n address lines, the CPU can use it to address 2ⁿ different memory locations.

The CPU Data Path

The CPU's data path (or data flow) is generally composed of:

• Registers (typically 1 to 32, depending on the architecture).
• The Arithmetic Logic Unit (ALU).
• Internal buses that interconnect these components.

Instruction Types

Instructions executed by the CPU often fall into categories such as:

• Register-Memory instructions.
• Register-Register instructions.

The CPU Instruction Execution Cycle

The CPU executes instructions sequentially in a series of small, defined steps:

1. Fetch: Locate the next instruction in memory and place it in the Instruction Register.
2. Increment PC: Modify the Program Counter (PC) to point to the subsequent instruction.
3. Decode: Determine the type of instruction that has been fetched.
4. Address Calculation: If the instruction uses a data word in memory, determine its location (address).
5. Operand Fetch: Fetch the word if necessary and place it in a CPU register.
6. Execute: Perform the operation specified by the instruction.
7. Loop: Return to Step 1 to begin executing the next instruction.