CPU Operations: Interrupts, I/O, DMA, and Multiprogramming

Program Counter (PC) and Instruction Register (IR)

The Program Counter (PC) contains the address of the instruction to be read. The Instruction Register (IR) contains the last statement read.

Interrupts

Interrupts interrupt the normal execution of the processor. They appear mainly as a way to improve processing efficiency. Interrupts can be generated by software, clock, I/O, or hardware failure.

Disabled Interrupts

Disabled interrupts mean that the processor will ignore the interrupt signal. If an interruption occurs during that time, it generally will remain pending and will be checked by the processor after it enables interrupts.

Processor Actions

When the processor interprets the instruction and performs the action, the action can be classified into the following four categories:

• Processor-memory: Data is transferred from the processor to memory or vice versa.
• Processor-I/O: Transferring data to or from a device in a peripheral, performing the transfer between the processor modules and I/O.
• Data processing: The processor performs some arithmetic or logic operation on data.
• Control: The statement calls for altering the execution sequence.

Interrupt Handling Routine

When an I/O device is available, i.e., when it is ready to accept more data from the processor, the I/O module of the device will send an interrupt request to the processor. The processor suspends the operation of the current program and jumps to a program that serves the I/O device, known as the interrupt handling routine, and returns to the original performance after attending to the device.

Multiprogramming

Even with the use of interrupts, a processor may not be taking advantage of resources in a very efficient way. For example, if the time needed to complete an I/O operation is much greater than the user code between I/O calls, then the processor will be idle for much time. One solution to this problem is to allow multiple user programs to be active at the same time.

Scheduled I/O

The processor issues an instruction to the I/O. It generates a command to the appropriate I/O module. The processor takes an active role while addressing the I/O instruction and periodically checks the status of the implementation of the I/O module until it verifies that it has completed the operation.

Problem: The processor spends a lot of time waiting for the completion of the I/O module, and the system is seriously degraded.

Solution: While attending to the I/O module, the processor can continue with useful work.

Interrupt-Driven I/O

An event that disrupts the normal flow of execution caused by an element external to the processor. It is an asynchronous event.

Problem: On large transfers to a device's memory or vice versa, it leads to excessive use of the processor.

Solution: Direct Memory Access. In a single command, it generates everything necessary for the transfer of information from memory to the device or vice versa.

Direct Memory Access (DMA)

Performed by a separate module connected to the system bus or included in an I/O module. Useful when the processor wants to read or write a data block.

Definition of Exception

An unexpected event generated by a condition that occurs during the execution of an instruction (e.g., arithmetic overflow, invalid address, privileged instruction, etc.). It is a synchronous event.

Dual-Mode Operation

What happens if a program accesses the host memory where the interrupt vectors are? What happens if you modify it? Solution: The processor has different modes of instruction execution:

• Privileged instructions (as supervisor/kernel): Those whose execution may interfere with the execution of any program or program of the OS (e.g., write to the port of a device).
• Non-privileged instructions (user mode): Those whose performance does not present a safety problem for other programs (e.g., increment a counter).

Stack

Used to control procedure calls and returns. The top is the point at which the stack can be accessed.

Procedure Calls and Returns

A common technique for handling procedure calls and returns is based on the use of a stack. When the processor executes a call, it places the return address on the stack. When it executes a return, it uses the address on the top of the stack.