Understanding Flip Flop and Multiplexer Designs in VHDL
Flip Flop XR
library ieee;
use ieee.std_logic_1164.all;
Entity FFXR is
Port( clk, x, r : in std_logic;
q: buffer std_logic);
End FFXR;
Architecture Behavior of FFXR is
Begin
Process
Begin
Wait until clk 'EVENT' and clk='1';
if x='0' then
if r='0' then
q <= not q;
Else
If r='0' then
q <= '0';
Else
q <= q;
End If;
End If;
End Process;
End Behavior;
Multiplexer 4-to-1
library ieee;
use ieee.std_logic_1164.all;
Entity Mux_4_1 is
Port(aB:...